Evaluation of p-GaN HEMTs degradation under high temperatures forward and reverse gate bias stress

In this study, the degradation behavior and physical mechanism of the p-GaN HEMT devices under high-temperature gate bias (HTGB) with +5 V and −5 V were investigated. The DC characteristics show that the device after forward HTGB stress exhibits an obvious negative threshold voltage (Vth ) shift, while the device after reverse HTGB exhibits a negligible shift. The following explanations could be given for the deterioration mechanism: a portion of the two-dimensional hole gas (2DHG) accumulated in the p-GaN layer at the p-GaN/AlGaN interface under long-term forward bias may fill the trap in the AlGaN layer through the tunneling effect. In addition, the drain-source on-resistance of the device had increased after +5 V HTGB stress, and a distinct decrease of accumulated capacitance was observed in the Cg -Vg curve. It indicates a degradation of the gate quality of the device after applying a forward-biased HTGB stress.


Introduction
Due to the high breakdown voltage, low on-resistance, high electron saturation rate, and many other high-quality characteristics, AlGaN/GaN high electron mobility transistors (HEMTs) are favored in modern electronics technology [1].Typical GaN HEMTs are normally-on devices, which is not ideal in industrial applications for fail-safe and energy saving.For normally-off (E-mode) operations, many studies have been suggested [2][3][4].Among them, the p-GaN HEMTs are a more interesting solution for E-mode operation compared to Cascode GaN HEMTs and recessed-gate MOSHEMTs.Generally, p-GaN HEMT devices are selected to stack a layer of Mg + doped GaN above the AlGaN/GaN heterojunction, with 2DEG depleted to acquire normal-off operation.As a result, the V th of p-GaN HEMTs devices can typically reach about +1.5 V, while achieving a high breakdown voltage and a high Baliga's figure of merit (  = V /  , ) [5].This technology has enormous commercial potential.
However, stacked p-GaN layers expose the device to new gate reliability issues.Under actual operating conditions, it is often necessary to have a positive gate voltage to switch the device on correctly and a negative gate voltage to switch it off completely, so it is important to evaluate the reliability of the p-GaN HEMTs under gate voltage bias.Although much work has focused on the p-GaN HEMT devices' V th instabilities with positive and negative gate bias [6], the degradation mechanisms of the device remain unclear.Therefore, studying the stability of the device under positive and negative gate bias at high temperatures and understanding their degradation mechanisms are essential for the development and application of p-GaN HEMT devices.
In this study, we investigated the reliability of p-GaN HEMT devices under long time forward and reverse HTGB stress.We measured and analyzed the electrical characteristics of the devices before and after stress and discussed the degradation mechanism of the device.The results may be helpful for the reliability improvement of p-GaN HEMTs.

HTGB test conditions
The forward and reverse HTGB tests were executed on the p-GaN HEMT devices, respectively.The high-temperature forward gate bias voltage was +5 V, and the high-temperature reverse gate voltage bias was -5 V.During this test, both source and drain electrodes were grounded.The experimental conditions are shown in Figure 1, with a temperature setting of 100°C and a duration of 336 h.

Effect of electrical characteristics
To investigate the precise impacts of HTGB stress on p-GaN HEMT devices, we measured and studied the electrical characteristics of p-GaN HEMT devices at 25°C before and after stress.The transfer (I ds -V gs ) curves of p-GaN HEMTs devices before and after -5 V and +5 V HTGB stress are displayed in Figures 3 (a) and (b), where V ds = 2 V and the gate voltage at I d = 1 mA is V th .As can be seen, the transfer curve of the device has essentially no drift after -5 V HTGB stress.In contrast, after 336 h of +5 V HTGB stress, the threshold voltage of the device shows a significant negative drift with the value of 150 mV.The variation of the device output characteristics before and after -5 V HTGB and +5 V HTGB stress is shown in Figures 4 (a) and (b), where V gs ranges from 2 V to 5 V in 1 V step.After a -5 V HTGB stress, the output current of the device remains essentially unchanged.However, after a +5 V HTGB of 336 h, the device saturation current increases significantly, with the value of I ds changing from 0.538 A to 0.578 A for V gs =5 V and V ds =3 V.It may be related to the negative drift of the threshold voltage.The p-GaN HEMT device shows strong stability under -5 V HTGB stress.V ds (V) @fresh @-@V@HTGB@ V gs :2V~@V step=1V V ds (V) @fresh @+@V@HTGB V gs :2V~@V step=1V (b) Furthermore, on-resistance was measured before and after stress at I d = 1 A. After 336 h of +5 V HTGB stress, the on-resistance of the device increased by 3.2%, as shown in Figure 5.According to the approximate resistance equation for p-GaN HEMTs devices, we have: where R C represents the total resistance of the source and drain, R 2DEG represents the total resistance of the 2DEG in the gate-drain and drain-source regions, and R 2DEG(GATE) represents the 2DEG resistance beneath the gate.We speculate that the increase in on-resistance after a +5 V HTGB stress may be related to an increase in R 2DEG(GATE) due to gate degradation.@.0 @.@6.0 6.@ 7.0 7.@ 8.0 V gs (V) @fresh @+@V@HTGB@ Figure 5. Drain-source on-resistance of the DUT before and after +5 V HTGB stress (@I ds = 1 A).
To confirm the above speculation, the gate capacitance characteristics of the device before and after +5 V HTGB stress were measured.During the measurements, the source and drain were grounded, and a 25 mV AC voltage was applied to the gate at a frequency of 1 MHz.The measured C g -V g is shown in Figure 6.It can be observed that when the gate voltage applied is smaller than the V th , the channel 2DEG is depleted, and the gate capacitance is small.With the increasing V gs , the channel gradually opens, and the gate capacitance value begins to increase gradually until saturation.When the device is fully on with V gs from +3 V to +5 V, there is a clear drop in gate capacitance.This phenomenon of lower accumulation capacitance for the device after +5 V HTGB indicates that the quality of the gate became poorer on account of the degradation effect of long-term forward stress [7].V g (V) @fresh @+@V@HTGB@ Figure 6.C g -V g curves of the DUT before and after +5 V HTGB stress.

Mechanism analysis
The drift of the threshold voltage can be explained by the accumulation of electrons and holes as well as the trapping of holes.Figure 7 shows the gate region energy band diagram of the device with a +5 V gate voltage.Under the bias of the forward gate voltage, a fraction of 2DEG's electrons entered the p-GaN layer by crossing the AlGaN potential barrier layer.A large number of holes are collected in the bottom of the p-GaN layer to form 2DHG and a small number of them are trapped by defects in the AlGaN layer through the tunneling effect.At the same time, the number of holes trapped by the defects is already significant after a long period of positive HTGB stress of 336 h.After the stress is removed, the trapped holes are not released in time, resulting in a negative drift of threshold voltage.

Conclusion
In conclusion, obvious performance degradation of the p-GaN HEMT device was observed after +5 V HTGB stress over long periods, while -5 V HTGB stress had an insignificant effect on the device.A positive drift of nearly 150 mV in the threshold voltage and a 40 mA increase in the saturation current were found after the +5 V HTGB stress, which could be related to the holes trapped in the AlGaN layer under long-term positive gate bias.In addition, the drain-source on-resistance increased, and the accumulated capacitance in the gate region decreased obviously after the stress, indicating that the gate quality of the device deteriorated after the forward HTGB stress.

Figure 1 .Figure 2 .
Figure 1.Experimental conditions of HTGB with negative bias and positive bias.Both source and drain electrodes were grounded.

Figure 3 .
Figure 3. (a) Transfer curves of the DUT before and after -5 V HTGB stress.(b) Transfer curves of the DUT before and after +5 V HTGB stress.

Figure 4 .
Figure 4. (a) Output curves of the DUT before and after -5 V HTGB stress.(b) Output curves of the DUT before and after +5 V HTGB stress.

Figure 7 .
Figure 7.The p-GaN HEMT Energy band diagram of the gate region with +5 gate voltage.