A Bootstrap Drive and Level Shifting Method for Buck-boost Converter with NMOS as the Main Switch Transistor

In the design of DC-DC power supply, compared with a P-type metal oxide semiconductor field effect transistor (PMOS) with the same width-to-length ratio, N-type metal oxide semiconductor field effect transistor (NMOS) as the main switching transistor greatly reduces the on-off loss and improves the conversion efficiency of the system. This article introduces a gate voltage bootstrap and level shifter circuit for a Buck-Boost DC-DC converter with NMOS main switching transistor. The drive voltage between the gate and the source pole of the main switch transistor can be stabilized, which is independent of the switch junction voltage (V SW) and solves the problem that the drive voltage of the gate is too high or too low due to the influence of the bootstrap voltage in the traditional structure. Based on the 0.18 μm BCD process, the circuit design and physical implementation of the proposed method are verified. The test results show that the bootstrap drive circuit functions normally and the bootstrap drive voltage is about 5 V when the input voltage is 2.9~4.5 V and the output voltage is −2~-5 V. In addition, the proposed gate-level shifting circuit can reduce the drive delay of the main switch transistor to less than 12 ns.

1. Introduction DC-DC power supply is widely used in portable electronic devices because of its advantages of high efficiency, large output current, and small static current [1].At present, N-type metal oxide semiconductor field effect transistors (NMOS) are used as power transistors in many high-voltage application circuits.NMOS transistors have the characteristics of higher mobility than P-type metal oxide semiconductor field effect transistors (PMOS).Under the same size conditions, NMOS transistors have smaller on-off resistance, to improve the efficiency of DC-DC power supply [2][3][4].However, it is necessary to solve the gate voltage driving problem of NMOS power transistors accordingly.Otherwise, the gate-source voltage driving is not enough, which will lead to an increase in the conduction impedance of the power transistor and increase the conduction loss [5][6].
At present, self-lifting booster drive technology has been widely used because of its simple method and low power consumption, which mainly includes two parts: bootstrap driver and level shifter.However, in the existing technologies, the gate drive voltage is too high or too low due to the influence of the boost voltage on the switch junction voltage (V SW ) or input voltage (V in ), and the level shifter circuit cannot timely transmit the drive voltage to the NMOS gate, resulting in too much drive transmission delay [7].In addition, in Buck-Boost converters, since the output voltage (V out ) is negative, the level shifter circuit needs to quickly switch back and forth between negative voltage and higher bootstrap voltage, which makes the circuit design more difficult.Based on the above analysis, a gate bootstrap driver circuit based on Buck-Boost is proposed, which solves the problems of unstable driving voltage and long delay of the level shifter.

Traditional bootstrap driver
The traditional bootstrap driver circuit is simple in structure and widely used, and its structure principle is shown in Figure 1.
Figure 1.Traditional bootstrap driver M N1 is the main switch transistor of the NMOS type, and M N2 is the continuation transistor.There is a capacitor C BST with large resistance between BST and SW point, and the voltage difference between the two points is the bootstrap charging voltage V BS .After the continuation transistor, M N2 is closed, and this voltage will act as the gate-source voltage of M N1 , thus driving M N1 to open.Its working principle is divided into two stages: charging stage: when TG is low level, the gate of M N1 switches to SW end through level shifter circuit, M N1 is off, and then V SW is approximately equal to V out (V out is negative voltage) because M N2 is switched on, and the input voltage V in charges the charging capacitor C BST through a single wizard pass diode.Discharge stage: when the TG level is high, the gate of M N1 switches to the BST terminal through the level shifter circuit.Since M N2 has been turned off, M N1 is switched on, V SW is approximately equal to V in , and the SW voltage jumps.Since the voltage difference between the two ends of the capacitor does not mutate, the voltage of V BST is raised at this time, D is cut off, and M N1 is kept on.In this process, the charge needs to increase the gate voltage of the power transistor, and M N1 is all provided by the capacitor C BST , so the value of the capacitor C BST is usually large.
According to Figure 1, the equation of the bootstrap driver circuit in the capacitor C BST charging stage is: where V D is the positive pilot voltage of the diode; V BS indicates the voltage difference between the two sides of C BST.
This voltage will be used as the gate-source voltage of the main switching transistor during the discharge phase.As can be seen from Equation (2), the voltage difference is determined by the V SW in the continuation phase.

The circuit design of high stability bootstrap drive voltage
The voltage difference between the two ends of the charging capacitor in the traditional gate bootstrap driver is determined by the V SW , and too high or too low voltage at the SW point will affect the loop.The bootstrap driver circuit designed in this article can stabilize the differential pressure V BS at both ends of the capacitor, to improve the stability of the system loop.Figure 2 shows the designed bootstrap driver circuit.
Figure 2. Schematic of proposed bootstrap driver M P1 and M P2 form the PMOS current mirror, I 1 is the bias current of the circuit, and M N4 is seven diode-connected NMOS transistors in series.If the gate-source voltage of a single diode-connected NMOS transistor is V gs1 , the gate voltage of M N4 is 7V gs1 , and the source pole of M N4 is connected with the output voltage V out , the input voltage V in will be connected to the drain of M N3 through the diode D, and the source pole of M N3 will be connected to the BST terminal through the resistor R 1 .
It is supposed that the voltage between the gate and the source of M N3 is V gs2 .According to Figure 2, the equation of the bootstrap drive circuit in the charging stage of capacitor C BST is as follows.
The equation of V gs is: V BS indicates the voltage difference between the two sides of C BST : As can be seen from Equation ( 5), the final result of V BS of the boot-up drive voltage has nothing to do with the voltage at the SW end.The voltage difference between charging capacitors C BST is always 7V gs1 -V gs2 .The bootstrap driver circuit finally realizes the voltage at both ends of charging capacitors.C BST is constant, and V BS can adjust it to about 5 V.

Fast-level shifting circuit design
The function of the level shifter circuit is to convert the low voltage control signal TG into the level signal V G suitable for the high voltage driver device.The level shifter must have strong driving ability to meet the driving requirements of the output stage.At the same time, the level shifter circuit works at high voltage, requiring lower static current and faster conversion speed.The designed level shifter circuit is shown in Figure 3.

Figure 3. Schematic of the proposed level shifter
The TG end is the input end with high and low logic levels, and the GH end is V out +6V gs1 .When the TG input logic is high voltage level, M P3 is cut off and M P4 is switched on, so the voltage of terminal C is close to but lower than the GH voltage, and the end of C is pulled down to V out .At this time, the cross-coupled comparator on the right is pulled down to V BST due to the cut-off of M N10 , and all the tail current flows through the branch of M N9 .a point voltage is lower than b point voltage by a V gs voltage, resulting in M P5 and M N11 branch current, which causes that V o pulls down, so V G rose to V BST and the main switch transistor opens.When the TG input logic level is low, the V G is lowered to the V SW to turn off the main switch transistor.The function of R 4 and R 5 is to stabilize the voltage of a and b at the SW terminal during the jump, but a larger resistance value is needed to avoid the impact on the circuit.Because of the large voltage difference between V out and V BST , a high-voltage MOS transistor is needed in the circuit.

Simulation results and discussion
A Buck-Boost DC-DC power management chip is designed based on the 0.18 μm BCD technology.The overall design area of the chip is 2, 179 μm×1, 128 μm, and the layout area of the gate driver module is 119 μm×113 μm.At the TT process angle, the input voltage is 3.7 V, the output voltage is -2.7 V, and the temperature is 27℃.The bootstrap capability of the circuit is tested, as shown in Figure 4.According to the simulation results in Figure 4, in the stage of bootstrap capacitor charging, V SW is -2.7 V, V BST is 2.3109 V, and the difference between them by V BS is 5.0109 V.In the discharge stage of the bootstrap capacitor, V SW is 3.7 V, V BST is 8.6922 V, and the difference between them is 4.9922 V, about 5 V.
When the input voltage ranges from 2.9 V to 4.5 V, the V BS voltage is simulated and verified.The verification results are shown in Figure 5.The minimum value of V BS is 4.989 V, the maximum is 4.994 V, the maximum difference is 0.005 V, and the change rate is 0.10%.When the output voltage ranges from -2 to -5 V, that is, the V SW ranges from -2 to -5 V, the V BS voltage is simulated and verified.The verification results are shown in Figure 6.The minimum value of V BS is 4.982 V, the maximum is 5.055 V, the maximum difference is 0.073 V, and the change rate is 1.44%.Under the typical value conditions of input voltage 3.7 V and output voltage -2.7 V, the capacitance of the parasitic gate capacitor is 22 pF.The drive delay time of the main switch is verified, and the results are shown in Figure 7.It can be concluded from the data in Figure 7 that the ascending transmission delay (t up ) is 11.964 ns, and it can be concluded that the designed level shifting circuit generates a drive transmission delay of less than 12 ns.
Table 1 is a comparative analysis of the circuit designed in this article and the related parameters of the bootstrap driver circuit used in [8][9][10].It shows that the circuit in this article has great advantages.a Note: "-" indicates no discovery.

Conclusions
Through simulation verification and comparison of relevant data, it can be seen that the bootstrap driver circuit proposed in this article can realize that V BS is independent of V SW , and can solve the problem of too high or too low gate drive voltage caused by the influence of V SW on traditional V BS .
V BS can reach 5 V, which can meet the driving needs of NMOS power transistors.The designed level shifter circuit makes the driving transmission delay of the main switch transistor less than 12 ns.This circuit has been applied in a Buck-Boost converter.

Figure 6 .Figure 7 .
Figure 6.V BS corresponding to different output voltages