A power constant logic circuit based on mask control

As the structure of existing anti-power attack circuits has certain security problems, this paper proposes a new mask-based control constant power logic circuit based on the existing masking technology. By integrating OR/NOR and AND/NAND circuits into a dual-rail circuit, different circuit logic functions can be controlled by inputting different masks. By introducing two parameters, Normalised Energy Deviation (NED) and Normalised Standard Deviation (NSD), the structure proposed in this paper improves the level of resistance of the circuit to power attacks to a certain extent, as well as reduces the cost of the circuit compared to other power attack resistant circuits.


Introduction
In 1998, Kocher et al. proposed the theory of side-channel power analysis attack [1] .A power analysis attack is a non-intrusive side-channel attack technique that aims to obtain the non-public key used in cryptographic chips.According to the different analysis methods and attack strengths, power attacks can be categorized into simple, differential, and high-order differential power attacks [2][3][4] .Among them, the differential power consumption attack is based on statistical analysis, which can greatly reduce the noise effect caused by power consumption and poses a great threat to cryptographic chips.To address this problem, researchers have developed a series of countermeasures against DPA, which are mainly categorized into algorithmic and circuit levels.Circuit-level countermeasures aim to make the power consumption generated by the cryptographic module independent of the data being processed.For example, there is the adiabatic logic structure [5][6] , the dual rail logic structure [7][8][9] , the wave dynamic differential logic (WDDL) circuit proposed by Tiri et al. [10] , the masked logic proposed by Golic [11] , the TEL circuit (Time Enclosed Logic) proposed by Bellizia et al. [12] , and the fluctuating power logic proposed by Zhang et al. [13][14] .Algorithm-level countermeasures are primarily introduced by incorporating masking techniques into cryptographic algorithms and improving the reliability and security of the cryptographic algorithm.The introduction of masking techniques can cause the circuit's output to be randomly reversed, making it impossible for an attacker to obtain the correct output value.
In this paper, existing circuits against power attacks are experimentally simulated in Hspice, and it is found that some circuit structures do not achieve constant power consumption and are costly.Therefore, this paper proposes a new mask-based control of power-constant logic circuits and integrates the two logic structure circuits into a dual-rail structure, enhancing the circuit's ability to resist power consumption attacks while reducing its costs.

Related schemes
The basic structure of the Look-Up Table (LUT) unit proposed by Yue et al. [15][16] is shown in Figures 1(a Building upon the LUT structure, Yu et al. [17] introduced a mask to design a 3-AND gate Masked-LUT Based Differential Logic (MLBDL) circuit with three inputs in 2015.In this circuit, one input acts as a mask, and the other two inputs perform the AND logic structure functions.Figure 2 [18][19] .Figure 3 demonstrates the OR logic circuit structure of the MDP 2 L single rail, which comprises two parts, left and right.The upper part of the left circuit is used to realize the logic function of the OR gate, while the lower part is used to realize the logic function of the NOR gate.

Mask-based control of power-constant logic circuit design
This paper proposes a novel mask-based power constant circuit to address the power consumption imbalance generated by circuits processing varying data.Traditional dual-rail circuits, designed to resist power attacks, bundle a dual-rail structure with a single functional logic gate circuit (i.e., a tworail structure implementing a logic gate), which increases the number of MOS transistors and the average power consumption in the circuit.In contrast, this paper utilizes the distinctive properties of the mask itself to turn the MOS transistor on or off.The mask control is employed to implement two gate logic functions within a dual-rail structure (The logic functions OR/NOR gate and AND/NAND gate are implemented in this article).When the input signal (, ) is (0, 0), N2, N5, and N6 are turned on; when (, ) is (1,1), N1, N3, and N7 are turned on; when the input signal (, ) is (1, 0), N1, N6, and N7 are turned on; when (, ) is (0, 1), N2, N3, and N5 are turned on.Figure 5(a) depicts the MCPCL single-rail structure divided into left and right parts, with the right half constituting the power balance module.When the mask value m equals 1, the upper part of the left half is an OR gate; when the mask m equals 0, the logic function of the lower half is a NAND gate.Similarly, Figure 5(b) shows that when mask n equals 1, the upper part of the left half is a NOR gate; when the mask n is 0, the logic function of the lower half is an AND gate.Consequently, when masks m and n are both 0, the circuit can implement the AND/NAND logic function; when both masks are 1, the circuit executes the OR/NOR logic function.Moreover, MCPCL can serve as a circuit structure with a single logic function when the mask value (, ,  ,  ) in the circuit is one of the four cases (1, 0, 0, 0), (0, 1, 0, 0), (0, 0, 1, 0), and (0, 0, 0, 1).

Comparison of circuit security
According to the power consumption formula   * , the power consumption () is only related to the current () if the voltage () is uniquely determined.Therefore, the current curve measured in the experiment can reflect the relationship between the power consumption and its size.
Figure 6 presents a comparison of the MDP 2 L, LBDL, MLBDL, and MCPCL structures based on the same experimental environment and parameters.The input signals (a, b) were (1, 1) for a sampling time of 5 ns, (0, 0) for a sampling time of 10 ns, (0, 1) for a sampling time of 15 ns, and (1, 0) for a sampling time of 20 ns.The introduction of two parameters, normalized energy deviation (NED) and normalized standard deviation (NSD) [20] , further demonstrates that the MCPCL structure has better resistance to power consumption attacks.

𝑁𝐸𝐷
. ( The Normalised Standard Deviation (NSD) is defined as: where  is the standard deviation, defined as: show the instantaneous currents measured at different times for the LBDL, MDP 2 L, MLBDL, and MCPCL structures used as single logic gate circuits.Based on the data in Tables1-4, it can be observed that the MCPCL exhibits lower power consumption than the MDP 2 L, LBDL, and MLBDL structures when used as an input mask control circuit for a single logic gate.
According to the data in Table 5, the MCPCL structure has a lower NSD and NED than the LBDL structure, except for the NOR gate circuit.
Since MDP 2 L, MLBDL, and the MCPCL proposed in this paper are circuit structures that introduce masks, a comprehensive comparison of the masked circuit structures for both logics was conducted.It is assumed that m=0, n=1, and all other experimental conditions remain the same as in the above experiments.The data in Table 6 compares the power consumption magnitudes of the three circuit structures when MDP 2 L and MCPCL are taken into account for the role of the mask (assuming m = 0 and n = 1).From Table 6, it can be seen that the MCPCL structure reduces the NED by 38.2% and 36.6% and the NSD by 57.7% and 38.7%, provided that the average energy consumed for signal conversion is reduced by 45.6% and 41.4% compared to MDP 2 L and MLBDL, respectively.The smaller the NED and NSD are, the higher the level of resistance to power consumption is; therefore, the MCPCL structure proposed in this paper has a better level of resistance to power attacks compared to the comparison scheme.As shown in Table 7, the number of MOS tubes required to form an OR-NOR or AND-NAND gate circuit is 12 for the MCPCL structure, 24 for the LBDL structure, and 26 for the MDP 2 L and MLBDL structures, resulting in a circuit area of 50% less for the MCPCL than the LBDL and 53.8% less for the MDP 2 L and MLBDL.The MCPCL structure reduces the circuit cost to a certain extent.

Conclusion
This paper proposes an improved masked circuit, MCPCL, which integrates two logic structures into a dual-rail structure.Compared to MDP 2 L and MLBDL, the average power consumption of the proposed logic structure is reduced by 45.6% and 41.4%, respectively, while the number of transistors is reduced by 50% and 53.8%, respectively.Additionally, the NED is reduced by 38.2% and 36.6%,respectively, and the NSD is reduced by 57.7% and 38.7%, respectively, compared to existing masked anti-power analysis circuits.Based on the data obtained from Hspice simulations, the MCPCL proposed in this paper has effective resistance to power consumption attacks and provides better security for cryptographic chips in terms of area and power consumption.

Figure 1 .
Figure 1.Structure of the LUT, (a) OR LUT unit, (b) NOR LUT unit

Figure 2 . 3 -
Figure 2. 3-AND gate MLBDL circuit Figure 3. MDP 2 L single-rail OR logic circuit MDP 2 L (masked differential pass-transistor pre-charge logic) is a mask-based differential passtransistor pre-charge logic circuit proposed by Yao et al. in 2022[18][19] .Figure3demonstrates the OR logic circuit structure of the MDP 2 L single rail, which comprises two parts, left and right.The upper part of the left circuit is used to realize the logic function of the OR gate, while the lower part is used to realize the logic function of the NOR gate.

Figure 4 .
Figure 4. Components of MCPCL structure, (a) Single-rail OR/NOR GATE, (b) Single-rail AND/NAND GATE, (c) Power consumption constant module To eliminate the non-constant power consumption in the MCPCL circuit due to the different load capacitance of the complementary output signals, the constant power consumption module is introduced, as shown in Figure 4(c).

Table 1 .
AND-GATE data comparison.

Table 5 .
Comparison of NSD, NED for LBDL and MCPCL