Composite Gate Oxide Method for Improving the Reliability and Leakage Performance of Deep Submicron CMOS Processes

This article aims to address the issues of gate oxide reliability failure and leakage loss in SRAM circuits caused by the introduction of additional high-voltage devices in the 90 nm standard process. It investigates the corner thinning phenomenon using different gate oxide scheme. It analyzes the corresponding relationship between composite gate oxide and reliability and tests the leakage of the SRAM circuit. Research has shown that the use of composite gate oxide can effectively improve corner thinning. The ratio of thermal oxide to HTO in composite gate oxide directly affects GOI/TDDB. At the same time, the use of composite gate oxide also decreases device leakage to a certain extent. The standby leakage of SRAM circuits(Isb) can be reduced from 200 nA to less than 10 nA.


Introduction
When the device feature size scales down to 0.11 um or below, according to the constant electric field theorem, the operating voltage of standard devices is about 1.2-1.5 V.With the increasingly widespread application of high-voltage devices in the automotive electronics field, more and more customers need to introduce high-voltage devices (operating voltages 5 V) to sub-100 nm process in addition to standard 1.5 V devices.
The introduction of an additional HV device has brought about a series of reliability and yield risks [1].Firstly, high-voltage devices require thicker gate oxide.As the thickness of gate oxide increases, the phenomenon of active area corner thinning caused by thermal oxidation becomes increasingly severe [2][3], which greatly reduces the working life of related HV devices.The HV device reliability assessment of GOI/TDDB cannot meet the requirements [4][5].Secondly, the increase in the thermal budget caused by thicker gate oxide will lead to the sustained growth of substrate intrinsic dislocations or defects, which has a particularly significant impact on the leakage performance of the short channel 1.5 V devices [6].The final result is that the stand-by leakage of the SRAM circuit is too high to function.
This paper aims to solve the problem of reliability failure and leakage loss.The second part briefly introduces the experimental conditions and testing methods for reliability and leakage evaluation.The third part analyses and discusses the experimental results.Results demonstrated the validity of the new process in improving reliability and leakage issues.

Experiment
The purpose of the experiment is to address the reliability risks and leakage issues caused by the introduction of HV devices in the sub-100 nm standard processes.The operation voltage of the core device is 1.5 V, and the additional high-voltage device introduced is a 5 V device.The gate oxide thickness of 1.5 V devices is 20 A, and the gate oxide thickness of 5 V devices is 130 A. Both are grown using the wet oxygen method.The key parameters of the process are shown in Table 1.As mentioned on the previous page, due to the thermal oxidation characteristics, there exists a serious phenomenon of corner thinning in the thick gate oxide.As shown in Figure 1, the gate oxide thickness in the body region is 140 A, while the minimum gate oxide thickness in the corner region is only 66 A. The corner thinning issue greatly reduces the process reliability of thick gate oxide.On the other hand, the higher thermal budget brought about by thicker gate oxide will lead to faster surface conduction of stacked dislocations and defects in the substrate area.It has a decisive deterioration effect on the leakage performance of 1.5 V short-channel devices.
The experiment split structure list as below in Table 2.We focus on different materials of the composite gate oxide and different growth modes of the thick gate oxide and analyse their effects on reliability and device leakage performance.The reliability of gate oxide was evaluated through GOI and TDDB test.The GOI testing method applies RAMP voltage to the gate and substrate terminals of the device until the gate oxide breaks down [7][8].GOI tests the overall integrity of gate oxide and the defects or impurities introduced in the process to characterize the integrity of gate oxide electrical performance.The testing method of TDDB is to add a constant voltage to the gate and substrate terminals of the device at high temperature (ambient temperature 125℃) until breakdown [9].The time to failure (TTF) is confirmed, and then the device lifetime is calculated based on the acceleration factor.The test data of GOI and TDDB were processed and analyzed using Weibull distribution.
The device leakage performance is evaluated by testing the SRAM Cell-related stand-by leakage.SRAM adopts the commonly used 6T structure [10], 3D schematic and top view of SRAM refer to Figure 2.The testing method is to let the IC perform an initial test pattern.IC is put into a state of no action, and then DPS is used to read the total cell current (Idd) to characterize the leakage performance.

Results and discussion
This experiment used various gate oxides for research, including dry oxide, wet oxide, high temp oxide (HTO), and composite oxide.The materials and reaction mechanisms of different gate oxides are shown in Table 3. Dry oxide has good uniformity, repeatability, strong masking ability, and good adhesion to photoresists, but the growth rate is slower [11].Wet oxide has a fast growth rate but a loose structure, poor masking ability, and many defects [12].HTO is generated through chemical vapor deposition at high temperatures rather than through thermal oxidation.It does not require the consumption of silicon [13][14].The composite gate oxide in this experiment is formed by stacking dry oxides and HTO.Composite oxide Dry oxide stack HTO

Corner thinning of different GOX scheme
The principle of gate oxide thermal oxidation growth is that the oxidant penetrates SiO 2 and moves towards the SiO 2 -Si interface, and reacts with Si.The reaction kinetics follow the Deal Grove model.Due to stress concentration, the interfacial oxidation rate in the corner region is slower than in the body area.The corner thinning phenomenon is an inevitable feature of thermal oxidation reactions.On the other hand, HTO(high temp oxide) adopts the method of chemical vapor deposition, which does not require the consumption of silicon.The corners and the bulk region are completely the same, so theoretically, there should be no gate oxide thinning of the corners.The final electrical thickness of the different gate oxide structures we studied is approximately 140 A. Figure 3 shows the TEM micrograph of the corner and bulk region gate oxide using different structures.It can be seen that there is no corner thinning phenomenon of using the pure HTO structure, and even the gate oxide thickness in the corner region is thicker than that in the bulk region.The thinning phenomenon of the dry oxide + HTO scheme is relatively small.Meanwhile, the thinning phenomenon of the wet oxide structure is already quite obvious.The corner thinning phenomenon of the dry oxide structure is the most severe.
The thickness of the gate oxide at the corner is less than half of the body area.At the same time, we also analyzed the GOI performance of different ratios of dry oxide stacked HTO in a given thickness of composite gate oxide.Table 4 lists the total oxide thickness of the corner region corresponding to different ratios of dry oxide stacked HTO conditions and the corresponding Vbd data.It can be seen that Vbd is approximately linearly correlated with the total thickness of corner area, as shown in the trend chart in Figure 5.At the same time, Figure 5 also proves that GOI is not sensitive to material changes in gate oxide

TDDB result discussion of different GOX scheme
The TDDB testing structure only has one area mode.Normally the lifetime of the TDDB should be positively correlated with the thickness of the GOX. Figure 6a compares the TDDB lifetime of different gate oxide structures.The histogram of Figure 6a shows that under the same stacked oxide thickness, the lifetime of dry oxide and wet oxide structures is almost the same.In contrast, the lifetime of composite gate oxide structures is significantly lower than that of thermal oxide structures.In addition, there are significant differences in the TDDB lifetime of composite gate oxides with different Dry Oxide to HTO ratios [18].The reason for this phenomenon is speculated to be that both dry and wet oxides are formed through thermal oxidation, and their materials are relatively dense and have good resistance to degradation.And HTO is deposited through CVD, which may have unsaturated bonds and defects, and the material density is also worse than that of thermal oxide.
In the TDDB testing process, the HTO material cannot be equivalent to the thermal oxide of the same thickness.Here, we introduce the concept of "Effective TDDB Oxide Thickness".HTO is equivalent to the thermal oxide multiplied by an equivalent coefficient, which is between 0 and 1.The converted thickness is the effective TDDB oxide thickness.By analyzing the TDDB lifetime of different proportion composite gate oxide, the equivalent coefficient of HTO can be obtained by combining multiple formulas as 0.44.Based on the above data, we can derive an expected curve to accurately predict the TDDB lifetime using different gate oxide schemes, as shown in Figure 6b.In the formula in Figure 6b, x represents the thickness of thermal oxide, and y represents the thickness of HTO.The final TDDB lifetime is exponentially related to the effective TDDB oxide thickness.As can be seen from the diagram, the factors that determine the lifetime of TDDB include both the oxide thickness and the oxide material.This article evaluates the leakage performance by testing the standby leakage current (Isb) of a 4 M capacity SRAM circuit in standby mode.Figure 7 shows the percentage distribution of Isb for different gate oxide structures.The data shows that the leakage current of dry oxide and wet oxide schemes are much worse than that of composite gate oxide schemes.Considering that both dry and wet oxidation brings a greater thermal budget than HTO, this result is consistent with theoretical predictions.The Figure 7 graph data also indicates that using a composite gate oxide structure can reduce the Isb of SRAM circuits from 200 nA to around 5 nA, greatly improving the yield of SRAM.

Conclusion
In response to the reliability and leakage issues caused by the introduction of additional high-voltage devices in the sub-micro process, this paper proposes a process architecture of composite gate oxide.It systematically solves the reliability problems of thick gate oxide and the deterioration of leakage performance of low-voltage devices.The process structure is not only suitable for introducing the 5 V devices studied in this article but also for introducing higher voltage devices (>5 V) or high-voltage devices in smaller sizes (90 nm below) processes.
The results indicate that the GOI performance is linearly related to the thickness of the corner oxide and has little relationship with the oxide material.However, the TDDB performance is related to both the gate oxide thickness and the gate oxide material.In different ratios of the composite gate oxide, the equivalent coefficient of HTO is 0.44, which can be used to calculate the effective TDDB Oxide thickness.The TDBB lifetime can be accurately predicted based on the effective TDDB oxide thickness using the formula provided in this article.In addition, the leakage performance of composite gate oxide is also improved compared to normal thermal oxide structure.The standby leakage of 4 M SRAM circuits can be reduced from about 200 nA to below 10 nA.

Figure 2 .
Figure 2. a) 3D structural schematic diagram of SRAM with 6T architecture; b) Top view micrograph of SRAM with 6T architecture.

Figure 4 .
Figure 4. GOI Vbd Weibull distribution with different gate oxide scheme

6 Figure 5 .
Figure 5.The correspondence between Vbd vs. different ratios of dry oxide stack HTO

Figure 6 .
Figure 6.(a) TDDB lifetime comparison use different GOX scheme; (b) The effective TDDB Oxide thickness vs. TDDB lifetime3.4.SRAM leakage improve different GOX schemeIn this study, additional high-voltage devices were introduced into the standard process.It has brought about more thermal processes, increased the uncontrollability of dopant diffusion, and interfered with the formation of shallow junctions in the source/drain region.Ultimately, this leads to a sharp increase in leakage current for short-channel devices with standard processes (Channel length below 0.11 um).This article evaluates the leakage performance by testing the standby leakage current (Isb) of a 4 M capacity SRAM circuit in standby mode.Figure7shows the percentage distribution of Isb for different gate oxide structures.The data shows that the leakage current of dry oxide and wet oxide schemes are much worse than that of composite gate oxide schemes.Considering that both dry and wet oxidation brings a greater thermal budget than HTO, this result is consistent with theoretical predictions.The Figure7graph data also indicates that using a composite gate oxide structure can reduce the Isb of SRAM circuits from 200 nA to around 5 nA, greatly improving the yield of SRAM.

Figure 7 . 4 M
Figure 7. 4 M SRAM Istandby distribution chart with different gate oxide scheme

Table 1 .
The key feature of process parameters.

Table 2 .
Gox scheme summary table for experiment

Table 3 .
Material and reaction mechanisms of different gate oxide

Table 4 .
Total corner oxide thickness vs.