Design and Implementation of Beam Control System Based on FPGA

As the use of phased array technology becomes more widespread, it is receiving increased attention. Among them, the excellent performance of the beam control system will directly affect the performance of the whole phased array. FPGA is the preferred control chip for developing a beam control system. Therefore, this paper designs a beam control system architecture based on FPGA, designs the main functional modules of the system in detail, and conducts simulation experiments on its important functions. The results show that the system can quickly and accurately calculate the phase shift code required by the antenna unit to achieve fast beam response.


Introduction
In recent years, the phased array, as a new type of antenna, has received more and more attention and has been widely used in astronomy, modern communication systems, biomedicine, and other fields [1][2][3].As one of the key technologies in phased array antenna, beam control technology directly affects the system's performance [4].With the widespread use of phased arrays, the lightweight and miniaturization of phased array components, especially beam control systems, are required [5].Therefore, the design of a beam control system has high research value and broad application prospects in practical engineering.To meet the more functions of a phased array system, the beam control system needs to have the functions of data interaction, fast calculation, signal generation, data storage, and so on [6].With the development of large-scale integrated circuits, FPGA technology with high integration and parallelism has obvious advantages [7].Therefore, this paper studies the beam control of phased arrays based on FPGA technology.

Basic principle
A phased array antenna is an array composed of many radiation elements.As shown in Figure 1(a) of the rectangular array structure in a two-dimensional phased array [8], the number of array elements in the entire array is M*N, the spacing of the X axis between antenna array elements is d 1 , and the Y axis is d 2 .As shown in Figure 1(b), the direction cosine (cosx, cosy, cosz) can be used to represent the direction of the target.Then, the phase difference between two adjacent arrays can be divided into two directions of extended Z axis and extended Y axis, as shown in Equations ( 1) and (2), respectively: (2) By taking the array element with coordinate (0, 0) as a reference, the spatial phase difference between the (m, n) array element and the reference array element in the calculated array can be expressed as shown in Equation ( 3): By replacing the phase difference of the antenna array elements on the Z and Y axes with α and β, it can be expressed as shown in Equations ( 4) and ( 5): Then the in-array phase difference between the (m, n) antenna element and the (0, 0) antenna element can be written as shown in Equation (6): And because / 2 z a π θ = − , the angle between the target pointing and the Y-axis can be obtained as Equation (7): We set the amplitude weighting coefficient of the (m, n) antenna element as Equation ( 8), then the directional diagram function of the two-dimensional phased array antenna, as shown in Figure 1, can be expressed as Equation ( 8):

System design based on FPGA
The hardware platform of the phased array beam control system is the basis of beam synthesis and the key to ensuring the stable operation of the system [9].The hardware structure of the synthetic system designed in this paper is shown in Figure 2, which mainly includes the control module, beam transmitting module, signal receiving module, and data interface module.

Beam transmitting module
The transmitting circuit of the acoustic beam synthesis system controls the transmitting ultrasonic signal through FPGA.Then it forms a low-voltage analog signal after digital/analog conversion and low-pass filter.However, after the front-end processing of the transmitting circuit, the array element in the ultrasonic probe can be driven to transmit an ultrasonic signal.
Since the output waveform of the FPGA is a digital signal, the digital signal needs to be converted into an analog signal by a DAC converter.System design has high waveform accuracy and frequency requirements, so this design needs to choose a DAC conversion with high resolution, high precision, and high conversion speed and frequency.DAC902U [10] has an advanced segmented structure inside and has a very good dynamic range, which can provide audio signals for single-channel and multi-channel.With high impedance current output, the output rating range is 0~20 mA, and the maximum output voltage is up to 1.25 V. Differential output allows the use of differential or single-ended analog signal interfaces.Tight matching of current outputs ensures excellent dynamic performance in differential configurations.The input clock can be either 5 V or 3.3 V CMOS logic level.To improve performance, a clock signal with a duty cycle of 50% is required as the clock source input.The DAC conversion principle designed in this paper is shown in Figure 3.A total of 12 bits of D0 to D11 are directly connected to the pins of the FPGA as input data.PD is the DAC902U enable control pin.When the pin is high, the chip works and is also connected to the pin of the FPGA to facilitate the control chip.The CLK is the DAC902U input clock that drives the conversion of DAC data.
The analog waveform output by the digital-to-analog converter contains interference from other clutter signals, which will affect the synthesis of the beam, so the clutter signal must be filtered out.When the active filter is designed, the signal is at the input end of the operational amplifier.To ensure that the input and output of the filter have the same phase, we use the in-phase input.A second-order active low-pass filter is designed to filter out better high-frequency signal interference in the output end of the digital-to-analog converter, as shown in Figure 3.Because the received echo signal is weak, it is not easy to process, so amplifying the echo signal through the signal amplification circuit is necessary.In this paper, the AD835 amplifier is used, and its basic function is W=XY+Z, which can realize signal amplification with very few external devices.The front circuit is still an analog signal after conditioning.It needs to be converted into a digital signal after the FPGA chip recognizes an analog/digital (ADC) circuit.This paper uses ADS5520 analog/digital conversion chip.The chip has high system integration, and the parallel output of CMOS-level data ensures the compatibility of the interface.In this paper, the ADS5520 is a 12-bit streamlined ADC with a sampling rate of 125 MSPS.With a serial programming interface, at 100 MHz, the signal-to-noise ratio (SNR) is 70 dB, and the distortion-free dynamic range (SFDR) is 82 dB.The differential input voltage is small, and the chip analog power consumption is very low only 750 mW; A 3.

Control module
The control module uses feedback adjustment to control a series of operations of the phased array from signal acquisition to signal transmission, and its control process is shown in Figure 5.The control module initializes the phased array control parameters, sends the data acquisition command to the ADC unit, and the ADC acquisition unit initiates the data conversion and transmits the data back to the control module.After the control module obtains the data, the feedback adjustment algorithm calculates the DAC value corresponding to the phased array control parameters.The data of the ADC unit is transmitted to the DAC through LVDS to adjust the phase shift and direction, and the adjusted state is obtained again through the ADC acquisition board, and the control goal is reached in a cycle.

Wave control code calculation module
In phased array implementation, the calculation of wave control code is one of the important links.In this design, the off-axis Angle and rotation angle are used to define the beam-pointing angle of the antenna.The value range of the off-axis angle is [0 o , 45 o ], and the value range of the rotation angle is [0 o , 360 o ].The beam pointing of the antenna can realize conical scanning in the airspace.The antenna beam's normal direction is the coordinate system's Z-axis.
The calculation of wave control code includes the operation of a trigonometric function, multiplication and division of floating-point numbers, and superposition operation.For the operation of the trigonometric function, the search table is used to obtain the result because the technical protocol requires that the angle step of the antenna beam direction instruction is 0.01 o .The sine function value 0 o ~90 o can be stored in the FPGA ROM in the 0.01 o step.Because both sine and cosine functions can be converted into 0 o to 90 o of sine functions by trigonometric transformation, only 9001 values must be pre-stored in ROM.The decimal part of the sine function can be stored by multiplying the sine value by the N power of 2, which can ensure the precision of the wave control code operation.The division part of the processing can directly put the operation results into the operation flow to simplify the difficulty of FPGA operation.

Experimental tests
Wave control code is the most important data in the beam control, and the ModelSim simulation results of the wave control code calculation module are shown in Figure 6.When the signal interior_phase_ce signal is pulled high, the theoretical phase interior_phase signal begins to generate, and a new theoretical phase of the channel is generated after each subsequent clock cycle until the phase of all channels is generated.Once the interior_phase_ce signal is raised, the theoretical phase of the initial channel will immediately superimpose the compensated phase value.s_add1~s_add7 in the figure is the result of each step.The final signal ture_phase_index generated after angle normalization and wave control code conversion is the final wave control code to be output.Meanwhile, ture_ce will continue to increase during the generation of signal ture_phase_index.The simulation results of this module are in line with expectations.The output error characteristic of the DAC module is used as the basis for the system performance test.The standard resistance of 100 Ω is used as its output load for voltage and current measurement, and the linear error is shown in Table 1.It can be seen that the linear errors of several groups of current and voltage are small and stable.

Conclusions
Beam control affects the performance of the whole phased array.The beam control system is designed in this paper, and the simulation verification is completed.The test proves that the design method in this paper can effectively realize the beam control with small errors and has certain application significance.
Figure 1.Structure diagram of rectangular phased array

Figure 3 .
Figure 3. Low-pass active filter structure

Figure 4 .
Figure 4. High-pass active filter structure 3 V unipolar power supply can work normally.In this design, the input 19-pin INP and 20-pin INM must be connected to differential analog signals, ensuring high performance with a high sampling rate and input bandwidth.INP and INM are opposite each other.

Figure 6 .
Figure 6.Simulation results of wave control code calculation module

Table 1 .
DAC current and voltage error table