A 10-bit 160 MS/s Asynchronous SAR ADC design

This study describes a 10-bit 160 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) design in a 40 nm CMOS technical process. The SAR ADC is provided with an improved capacitive digital-to-analog converter (CDAC), and the capacitor array is featured by six split high-bit capacitors and a combination of splitting and monotonic switching schemes. This structure and switching scheme can both save power and improve speed while introducing negligible common-mode voltage change. An improved double-tail comparator and TSPC D flip-flops are implemented to further enhance the speed. Simulation results show that the ADC achieves SFDR 72.17 dB, SNDR 61.37 dB, and ENOB 9.90 bits at Nyquist input frequency. The power consumption of the ADC under a 1.2 V power supply is 2.808 mW, achieving 18.4 fJ/conv FoM.


Introduction
Analog to Digital Converter (ADC) plays an indispensable role in contemporary communication technologies as it connects analog signals with digital signals.As the signal frequency becomes higher, ADC is being pushed forward to become the direct front end to simplify the complexity of the system, which calls for ADCs with higher sampling rates and higher resolution.Successive Approximation Register (SAR) ADC is one type of ADCs that benefits most from the down-scaling of transistors because of its inherited merits of digital circuits.Compared to other ADCs, such as pipeline ADC and flash ADC, SAR ADC has a simple structure and uses fewer components.Thus, it obtains an optimal solution between area and power in high-speed applications.In recent years, benefiting from the research on the capacitive DAC(CDAC) architecture and switching schemes, SAR ADCs have become a better option for high-speed, low-power applications like sensors and biomedical devices [2][3] [4] .Among these switching procedures, Vcm-based switching procedures [3] and monotonic switching procedures [1] have become the most widely adopted choices.However, the Vcm-based switching procedure requires a Vcm voltage, which is becoming more challenging in low-power supply design.The monotonic switching procedure does not need a Vcm voltage, but it has a major drawback of causing a problem for comparator design because the common mode voltage changes constantly after each comparison.This article introduces a 10-bit 160 MS/s SAR ADC that has an improved CDAC.The split capacitors are combined with the monotonic switching scheme, and splitting and monotonic switching schemes are integrally used to resist the common-mode voltage change.An improved double-tail comparator is implemented to lower kickback noise and enhance speed under a low power supply.The traditional D flip-flops of the SAR Logic part are replaced by TSPC D flip-flops to further reduce the SAR logic delay.

SAR ADC architecture
The proposed SAR ADC comprises two sampling switches, a dynamic comparator, CDAC, and the SAR logic unit.Figure 1 demonstrates the framework of the proposed SAR ADC.The sampling switches are bootstrapped switches for high linearity under a low power supply.The CDAC utilizes the upper plate sampling technique, so the conversion can start immediately after sampling is finished.The split capacitors adopt the split monotonic switching scheme.The comparator is designed with an improved double-tail structure for high speed and low kickback noise.A high-frequency internal conversion clock is adopted in this design, and it is generated with the aid of the asynchronous SAR logic.
Figure 1.The framework of the designed SAR ADC.

Sampling switch
The speed and accuracy of the sampling part of the analog signal constitute the bottleneck of the overall speed and accuracy of the ADC to a large extent.The traditional sampling switch usually consists of a MOS transistor as a controllable switch and a capacitor as a memory.The circuit is simple and offers a rather small on-resistance.However, the on-resistance of the MOS transistor is dependent on the input voltage and causes the distortion of the sampled signals.Moreover, the charge injection effect also causes the voltage to be imprecise.To ensure high precision and linearity, a bootstrapped switch sampling circuit is designed, and its architecture is shown in Figure 2. The circuit works as follows.When CK=0, M1 is on, pulling node1 down to 0. M9 and M10 are on, pulling node2 down to 0. Thus, M5 and M6 are off, and M4 is on, pulling node3 to VDD.When CK=1, M10 is off, M1 is off, M2 is on, node4 is discharged to zero, and M7 is on, pulling node2 up to VDD.As a consequence, M5 is on, pulling node1 up to Vin.Because of the conservation of charge, node2 is pulled up to VDD+Vin, and the gate-source voltage of M10 remains unchanged and becomes irrelevant to the input voltage.

CDAC structure
Figure 1 shows the CDAC structure presented in this paper.It adopts six split high-bit capacitors and the split-monotonic switching scheme, which ensures the CDAC output is exempted from fluctuations of the common-mode voltage in the first six comparisons.The rest of the capacitors adopt the monotonic switching scheme.Figure 3 and Figure 4 manifest the voltage waveforms of the monotonic switching scheme and split-monotonic switching scheme, respectively.With this improved capacitor array, the total common-mode voltage change in this design is 98.4% less than that in the monotonic switching scheme.In this way, the design for the comparator would be greatly relaxed as such variation in common-mode voltage has negligible impact on the overall comparator performance.

Comparator design
This study employs a dynamic comparator to save power and reduce delay.Since the comparator operation is controlled by a clock, there is only dynamic power dissipation while no static power dissipation.The comparator adopts the structure in Liu et al.'s work [5] and is designed in the UMC 40 nm process.Figure 5 demonstrates the structure of the improved comparator.
The equation indicates that the delay is further reduced with lower VDD, which is more suitable for low-power supply design.

Asynchronous SAR logic and optimized delay
As depicted in Figure 6, the asynchronous SAR logic [7] works as follows.During the sampling phase, each of the D flip-flops output is reset to zero, and CMP_EN is low.CKC is thus low, and the comparator does not work during this period.When the conversion phase begins, the CMP_EN signal is high, CKC is pulled high, and the input voltage is compared through the comparator.Once the comparison is completed, the comparator outputs (OUTP OUTN) are pulled to different voltages.A simple NOR gate is implemented to generate the READY signal, and the CKC is pulled to low after a proper delay.The READY signal also triggers D flip-flops at the first row to generate the clock for D flip-flops at the second row, thereby storing the results of the comparator and controlling the CDAC switches.The propagation delay from the comparator outputs to the SAR logic output is typically equivalent to the delay of two D flip-flops.To reduce this delay, the TSPC D flip-flop with reset input is designed and implemented in this work, as demonstrated in Figure 7.This is a specific dynamic logic circuit that uses fewer transistors and requires only a single-phase clock, which can greatly enhance the speed [8] .
Figure 7. TSPC DFF with reset input

Circuit simulation
The SAR ADC is designed in the UMC 40 nm CMOS technical process, and circuit simulation is conducted in this study using the Cadence Spectre tool under a 1.2 V power supply.The data is processed by MATLAB.Figure 8 and Figure 9 manifest the FFT spectrums of the circuit.At 10.4688 MHz input frequency, the SNDR, SFDR, and ENOB are 61.03dB, 72.07 dB, and 9.85 bits, respectively.When the input frequency is 77.9688MHz, the SNDR, SFDR, and ENOB are 61.37 dB, 72.17 dB, and 9.90 bits, respectively.When the input frequency is 77.9688MHz, the total power dissipation is 2.808 mW, achieving an 18.4 fJ/conv FoM.Table 1 shows the comparison of key parameters between this study and three comparison works [2] [5] [6] .

Conclusion
This study introduces a 10-bit 160 MS/s asynchronous SAR ADC design with several improved features.
The CDAC designed in this paper is beneficial for stabilizing the common-mode voltage.Besides, it can also loosen the design requirements of the comparator.The internal high-frequency clock is generated using asynchronous SAR logic, which improves the ADC's speed and efficiency.An improved doubletail comparator and TSPC D flip-flop are designed to enhance speed.Results of the simulation demonstrate that the ADC attains a 61.37 dB SFDR, 72.17dB SNDR, and 9.90 bits ENOB at Nyquist input frequency.The total power dissipation of the ADC under a 1.2 V power supply is 2.808 mW, achieving 18.4 fJ/conv FoM.

Figure 3 .
Figure 3.The voltage waveform of the monotonic switching scheme.

Figure 4 .
Figure 4.The voltage waveform of the split-monotonic switching scheme.

Figure 5 .
Figure 5. Improved double-tail Comparator structure This is an improved double-tail comparator, which can lower the kickback noise and enhance speed.The delay of the comparator is expressed in Equation (1), where gm.eff represents the equivalent transconductance of the back-to-back inverters.

Figure 8 .
Figure 8. FFT spectrum with input frequency at 10.4688 MHz

Table 1 .
Comparison of parameters in different works