Design of a Ka-band power amplifier

This paper introduces the design of a type of power amplifier working in the Ka-band, which has three stages based on 45nm CMOS technology. The operating frequency is 25-27GHz, and it has good efficiency and linearity. Among them, the driving stage adopts a cascode structure, the power stage adopts common source structure, and the matching network adopts a transformer structure. Using Cadence Virtuoso for simulation at the operating voltage of 1.8V, power gain of the single-ended power amplifier is 44.76 dB, saturation output power is 14.66 dBm, the output power at the 1dB compression point is 12.9dBm, and corresponding power-added efficiency is 22.19%.


Introduction
Power amplifiers (PA) are designed differently than radio frequency (RF) small-signal amplifiers.On the one hand, due to the different performance indicators they pursue, small signal amplifiers consider more performance, such as gain and noise.Although the power amplifier also considers the power gain performance, due to its role in the RF transmitter, the design pays more attention to its output power (Pout), linearity and efficiency [1].In addition, the concept of impedance matching (or power matching) in the field of small-signal amplifiers is no longer applicable because its input and output signals are usually large signals.Therefore, considering the power at the output terminal and efficiency, matching network design which is shown in the power amplifier requires different design theories and implementation methods [1][2][3][4].
The frequency range of the Ka band, which is usually defined as 26.5-40GHz, and its frequency band is relatively wide [1].Compared with traditional 2.4 GHz or 5 GHz, it is suitable for faster transmission of required data and high-resolution radar imaging system.Although the increasingly common GaAs process has many advantages, such as relatively high V bk and relatively high frecut [2], with the development of complementary metal oxide semiconductor technology, power amplifiers using CMOS technology can not only reduce costs, but also integrate with other modules of transceiver system to achieve higher integration.This paper presents a CMOS power amplifier which works in the frequency range of 25 GHz to 27 GHz.The following is a brief introduction to the structure of this paper.Part two describes the calculation of transformer structure and matching network.The third chapter introduces the circuit implementation and simulation results of the schematic, and the fourth chapter gives the layout and postsimulation results of the whole circuit.Finally, the fifth chapter summarizes this design.

Power amplifier analysis
As an important part of power amplifier design, a topological structure is used to match the characteristic impedance (usually 50 Ω) to the required point on the Smith Chart [2].This chapter theoretically analyzes the matching network as a transformer structure.The network structure introduced in this chapter is composed of uncoupled resonant frequency, which replaces the inductance in the traditional matching network, the coupling coefficient k in the transformer structure, whose size reflects the coupling tightness between the two coupling coils, the quality factor, and the peak impedance, which replaces the resistance in the traditional matching network, as well as the capacitance [1].
In order to use the transformer structure in the matching network, the values of parameter of the transformer structure are required to be determined.Generally, to balance the output performance of PA considering both maximum gain and maximum power added efficiency (PAE), the impedance point with balanced performance can be obtained by the load-pull method [5].Load-pull technology is to measure and record the power and PAE at output end of 1 dB compression point by connecting different load impedances at the end of the structure in the simulation software or load pull equipment [6].The load impedance adjustment range should be large enough.Through the analysis of the simulation software, find the impedance points corresponding to different power on the Smith chart, calculate the P out and PAE of each impedance point, and finally find the load impedance with the highest P out and PAE.Then the contour map of P out and PAE can be drawn on the Smith chart, which is usually composed of a circle of contour lines with different colors, and the impedance points corresponding to the optimal output power and additional efficiency can be found [5][6][7][8].Figure 1 shows the topology of the output matching network of the designed transformer structure.

Schematic and simulation result
From the load-pull Smith Chart, to match the optimal point of load impedance (Zopt) with maximum output power and maximum additional efficiency, the values of each component of transformer are calculated and referred in figure 2. The calculation process is as follows: At this time, Conjugate the impedance and multiply by 50 ohms Z d = 76.5 − j31.5 (2) In this design, 150 fF is chosen for the initial guess C1.
It is calculated to be 229.5 fF, which means an additional 204.5 fF capacitance (C2) needs to be added in parallel with the 25 fF pad capacitance (CL) [1].After the drive stage, output stage and the value of each parameter of topological structure of the in/output network have been determined, inter-stage matching is performed.In the process of determining the circuit structure, according to the Smith chart, there are two circuit topologies to choose.The final circuit parameters are figure 3  In the layout design of integrated circuits, inductance occupies a large amount of chip area.The inductance of structure (a) is smaller than that of structure (b).With the same circuit performance, in order to reduce the layout area, structure (a) is finally used as the inter-stage matching [6].After all parameters and topology are determined, the schematic diagram of the design of three-stage power amplifier is presented in figure 4.

Vout
Pre-simulation results have demonstrated that at bandwidth of 25-27 GHz, the S11 parameter referred in figure 5, which means that the output port is 1 (reflected wave of port 1), and the input port is also 1 (incident wave 1 of port 1) [9][10][11], is smaller than -10 dB, which can indicate that the input and output impedance match well.The output power gain at port 2 (output port), referred in figure 6 is 44.76 dB.1dB compression point indicates the linearity of the whole design.The compression Pout of the threestage PA at 1 dB compression point (P1dB) referred in figure 7 is 12.9 dBm meanwhile the saturation compression point is 14.66 dBm.PAE indicates the time that the equipment can be used under a specific power supply.The PAE of 1dB compression point, referred in figure 7, is 22.19%.Bandwidth of a PA means a frequency range in which the power amplifier can provide sufficient power gain [9,12], usually maximum output power gain minus 3dB [13].It is expressed in Hertz, which is a concept of frequency.And 3 dB bandwidth is defined as the frequency range within 3 dB of the maximum gain value.As referred in figure 8, both 25 GHz (41.87dB) and 27 GHz (40.97dB) meet the requirements that the gain at this point is about 3dB less than the gain at the highest point (26.1GHz,44.35dB).Therefore, the bandwidth of this power amplifier is about 2 GHz.Through software of Cadence Virtuoso, the overall layout of the designed three-level PA is presented in figure 9, with an area of 0.741*0.522mm 2 .Post-simulation results demonstrate that at the bandwidth of 25-27 GHz, the S11 parameter referred in figure 10 is smaller than -10dB.The output power gain at port 2 (output port), which is referred in figure 11, is 41.43217 dB.1dB compression point is 11.29 dBm meanwhile the saturation compression point is 13.04 dBm, which are referred in figure 12.The PAE at 1dB compression point, which is referred in figure 12, is 19.55%.As referred in figure 13, both 25 GHz (37.91dB) and 27 GHz (36.9dB) meet the requirements that the gain at this point is about 3dB less than the gain at the highest point (26.2GHz,40.67dB).Therefore, the bandwidth of this power amplifier is about 2 GHz.
Compared to pre-simulation, the performance of post-simulation drops slightly.Among them, the output power gain is reduced by 3dB.The 1dB compression point, which symbolizes the linearity of the circuit, is reduced by 1dBm, and the power-added efficiency is reduced by 3%.Meanwhile, bandwidth remains largely unchanged.

Conclusion
This paper discusses the design of a power amplifier operating in a Ka communication frequency band with a bandwidth of about 2 GHz.In the part of the design of matching network, this paper theoretically analyzes one kind of unconventional transformer structure composed of uncoupled resonant frequency, coupling coefficient k, quality factor and peak impedance, and provides formulas for calculating these parameters.Based on these formulas, parameters of output matching network can be derived directly.Thanks to this unconventional design principle, a power amplifier based on 45nm CMOS process has been presented, which has the characteristics of high gain and high linearity compared with traditional matching networks, with simulation results of 44.76 dB power gain and 1dB power compression point of 12.9 dBm, which can be used in communication systems.

Figure 1 .
Figure 1. Circuit topology of output matching network.

Figure 2 .
Figure 2. Output matching network with parameters.

Figure 3 .
Figure 3. Topology of two inter-stage matching circuits.

Figure 4 .
Figure 4.The overall structure of the design of three-stage PA.

Figure 8 .
Figure 8. Bandwidth simulation of the design.