Simulation and optimization of metal gate CMOS process and circuit by TCAD

The feature size of CMOS transistors is shrinking as the semiconductor industry and technology advance. This phenomenon will have significant research implications for how to change device performance and maintain good performance. As a result, this paper completed a design and simulation of the CMOS process flow using TCAD. It was discovered through a qualitative analysis of the simulation results that the transfer and input characteristics of NMOS transistors decrease proportionally with the scale factor.


Introduction
Nowadays, microelectronic technology is developing in the direction of reducing the size of characteristic patterns, increasing the circuit density, improving the circuit speed, reducing the power consumption, increasing the size of chips and wafers, and reducing the defect density [1].At present, the standard CMOS process has entered the stage of 45-32nm, while the mainstream mature CIS processes are mostly concentrated at 180nm-90nm [2].The effective linewidth of the feature size of CMOS transistors has moved from the micron level to the nanometer level.For example, the CMOS process with a linewidth of 14nm recently released by Intel and the 55 nm CIS process based on Huali microelectronics [3].
In this paper, the process flow will be simulated by the TCAD tool to find out the method to adjust the device performance so that the performance of the metal gate CMOS device used can match the actual needs and be put into the actual production better.
The CMOS process has the advantages of low cost and easy compatibility with digital baseband circuits, and has significant advantages compared with other processes in many aspects, such as integration, heat dissipation, and cost [4].However, the current research difficulties in this field are mainly focused on improving the integration of metal gate processes, reducing the channel length and improving the device performance on the premise that the cost and process architecture remain unchanged.Under the conventional standard process, with the improvement of the integration and the continuous scaling down of the device structure, the stability of the device during operation will be reduced, and the protection structure without problems will also face serious challenges [5].In this paper, the TCAD tool is used to simulate the process flow, analyze the changes in various performances when the device size is reduced, and provide ideas for more process optimization methods.The device is fabricated on a p-type substrate, and two heavily doped n regions form the source and drain.The effect of the device occurs in the substrate region under the gate oxide layer.The source and drain in this structure are symmetrical.The size of the gate in the source drain direction is called the gate length L, and the size of the gate in the vertical direction is called the gate width W. Due to the lateral diffusion of the source/drain junction in the manufacturing process, the actual distance between the source and drain is slightly less than L. To avoid confusion, we define that L eff in the formula is called the effective channel length, L drawn is the total length of the channel, L D is the length of lateral diffusion.The effective channel length and oxide layer thickness play an important role in the performance of MOS circuits.Therefore, the main driving force in the development of MOS technology is to reduce these two dimensions generation by generation without degrading other parameters of devices.The potential of the substrate also has a great influence on the characteristics of the device, which means the MOSFET is an actual connection of a four-port device.As shown in Figure 1., it is always realized by a p + ohmic region [6].

Theoretical analysis of device performance
When it comes to the analysis of MOS structures, various simplified assumptions are usually introduced, but some of them are not valid in many analog circuits.For small-sized devices, it is necessary to understand the ideal scaling theory of MOS transistors [7].This paper will introduce some key factors and their effects on the performance of the simulated devices.

Threshold voltage
The threshold voltage is one of the important parameters of MOSFET, which is defined as the gate voltage when the substrate surface under the gate begins to undergo strong inversion, usually abbreviated as V TH .The threshold voltage of a field effect transistor (FET) is the minimum gate source voltage V GS required to create an on-path between the source and drain.It is an important scaling factor to maintain power efficiency.When referring to junction field effect transistors (JFETS), the threshold voltage is usually referred to as the pinch off voltage.

Scaling down theory
All lateral and longitudinal dimensions of MOS devices are reduced by k times (k > 1), while the threshold voltage and power supply voltage are reduced by K times and all doping concentrations are increased by k times.Since all the electric fields in the transistor are constant, the constant electric field is scaled down.After scaling down, the saturated leakage current can be expressed as: Although the saturation current drops to its times, the corresponding capacitance and power consumption will also be reduced, which is the advantage of scaling down.The total channel capacitance is as follows: The drain/source junction capacitance is also reduced by the same multiple through the proportional reduction of the total width of the depletion layer [8].

Small size effect
When the channel length is less than 3 μm, the small-scale effect is generated because it deviates from the ideal scaling theory, which means the power supply voltage does not scale down to cause the increased electric field.In addition, the built-in potential cannot be changed proportionally, but it cannot be ignored.The junction depth of the drain / source is not easily reduced.The mobility decreases as the concentration of substrate doping increases.The subthreshold slope cannot change proportionally either [9].

Velocity saturation.
In the analysis of long-channel MOSFETs, it is assumed that the mobility is constant.In this ideal case, the carrier speed will always increase and finally reach the required current.But in small-sized devices, when the transverse electric field reaches 1V/ μm, the mobility will begin to decrease.
When the electric field is strong enough, the carrier velocity V will reach a saturation value v sat , about 10-7 cm/s.The modified saturated leakage current characteristic can be approximately described as:

Channel length modulation.
When the MOSFET is biased in the saturation region, the depletion region of the drain extends laterally into the channel, thereby reducing the effective channel length.The space charge region of △L did not begin to form until V DS >V DS(sat) .As the first approximation to △L: As the leakage current is inversely proportional to the channel length, it can be concluded that I′ D is the actual leakage current.Since △L is a function of V DS , I′ D is also function of V DS .The output impedance is no longer infinite, and the leakage current in the saturation region can be concluded as λ is the channel parameter modulation coefficient.The current voltage characteristic curve is corrected [10].

Process flow design
The process flow design is based on NMOS process, and the software Silvaco_Tcad is used to repeatedly run the program to make the device parameters reach the same effect as described in this paper.

Device performance analysis and optimization
The transfer characteristic curve and output characteristic curve during the operation of the device are important performance indicators when evaluating the device performance [11].In this paper, the constant electric field of NMOS devices is scaled down and simulated to observe the performance of NMOS under different structures and parameters.

NMOS performance analysis with 𝐿𝐿 𝑠𝑠𝑒𝑒𝑒𝑒 =2μm
After the process flow design is completed, the program is compiled and debugged with TCAD, and finally the channel width of NMOS device reaches 2μm.
The doping distribution is as follows:

Influence of scaling down on transfer characteristic curve
The relationship of I D -V GS of CMOS is: When the scaling factors of k = 0.5 and k = 0.25 are taken, it can be obtained that I should increase proportionally with the decrease of k.It can be found that with the decrease of k (the equal scale reduction of the device), the I D of the device also increases.

Effect of scaling on output characteristic curve
Theoretically, the output characteristic curve will be roughly divided into three parts: low voltage region, unsaturated region and saturated region.After comparing the three output characteristic curves, it can be found that the curve clusters of I D -V DS are similar under different scale factors k, except that V GS varies proportionally under different scale factors.

Conclusion
During the simulation test of equal scale reduction, from the simulation experiment results, it can be found that the transfer characteristics and input characteristics of NMOS transistors decrease with the proportional reduction of the scale factor.
Due to the design of the software, the gate voltage W is not scaled down in this paper.Therefore, the channel length is too short, resulting in the decline of the device performance index.In the real device optimization, selecting to scale down the gate voltage W at the same time will improve the device performance to a certain extent.

2 .
The structure and principles of devices NMOS and PMOS are used simultaneously in CMOS technology.