Pipelined Memristive neural network analog-to-digital converter

This paper designs a pipelined memristive neural network ADCs. Cascade the sub stages of memristive neural network ADC with pipeline structure to improve the conversion accuracy of memristive neural network ADC. First, the signal flow of the pipeline architecture is optimized, and the compatibility between the 4 bit memristive neural network ADC and the pipeline architecture is solved. Secondly, the application of random disturbance circuits in pipeline architecture was analyzed. Combining the calibration circuit with the pipeline DAC to reduce the power consumption of the calibration circuit. Finally, the circuit model of memristive neural network ADC is built and compared with the existing memristive neural network ADC. The results indicate that the pipeline structure ADC designed in this chapter has the advantage of adaptive calibration in terms of calibration function.


INTRODUCTION
Due to the limitation of Memristor accuracy, the ADC conversion accuracy of single-stage Memristor neural network is 4 bit, and the sampling frequency is 100 kHz due to the limitation of operational amplifier bandwidth [1] .Therefore, this chapter designs an 8-bit Memristor neural network ADC with pipeline architecture.First, the pipeline architecture cascades 4 bit sub stages to improve the effective conversion accuracy of memristor neural network ADC [2] .Without changing the architecture of the Memristor neural network ADC sub level, the sampling speed can be improved by increasing the bandwidth of the operational amplifier.Secondly, combining the hardware friendly random disturbance structure, we optimized the pipeline architecture, designed the working sequence of pipeline Memristor neural network ADC, and improved the adaptive calibration ability of Memristor neural network ADC.Finally, the 8 bit Memristor neural network ADC is compared, which shows that the random perturbation unit and ADC pipeline architecture improve the conversion accuracy and stability of Memristor neural network ADC.

2.1.Pipeline Structure
Compared with the traditional CMOS pipeline structure [3] , the pipeline Memristor neural network ADC has two differences.Firstly, except for the input of the first sub stage being a sample hold input, the input of other sub stages of the pipeline does not require a sample hold circuit.Due to the continuous input characteristic of Memristor neural network ADC converter, the adaptation error caused by capacitor charging and discharging in traditional CMOS is reduced during the continuous change As shown in Figure 1, 4N bit pipeline Memristor neural network ADC includes sample and hold circuit, N sub stages and time-sharing error correction module.Firstly, the sample and hold circuit of 4N bit pipeline Memristor neural network ADC is designed.Since the sampling frequency of the Memristor neural network ADC is 1.66 GHz, and the conversion bits are 8 bits, the design goal of the sample and hold circuit is 1.66 GHz, and the ENOB of the sampling circuit needs to be greater than 8 bits.This article adopts the existing gate voltage bootstrap switch for design.The schematic diagram is: As shown in Figure 2, when the CLK clock is low, the gate voltage bootstrap sampling circuit is in the hold state, and the Memristor neural network ADC performs the quantization process.Among them, M8 and M9 conduct, the voltage of node A is pulled down, the sampling switch MS is disconnected, and the holding capacitor C2 begins to discharge, while Vs begins to maintain the output.At that time, the clock CLK signal was high level, the gate voltage bootstrap sampling circuit was in the sampling state, and the Memristor neural network ADC was used for calibration.CLK controls M1 to turn on, resulting in M5 to turn on, causing the voltage of node A to be at a high level.The sampling switch MS is turned on, holding capacitor C2 to start charging, tracking the input level, and outputting the frequency Vs=Vin.
Secondly, ADC quantizes the output of the sample and hold module after passing the sample and hold module.The i-th sub level in the first N-1 sub level receives the input analog signal Vi-1 and processes it in two parts.One part is used as the input Vi-1 of the subtractor, and the other part is quantized to generate a 4-bit digital code through a 4-bit Memristor neural network ADC, and converted into an analog voltage Vdi through a 4-bit DAC.The input voltage Vi-1 of the i-th stage is subtracted from the analog output Vdi of the DAC, and the residual voltage Vi is obtained by amplifying the inter stage gain A.
Since the sub stage ADC is 4 bits, in order to meet the input signal requirements of the next sub stage Memristor neural network ADC, the inter stage gain A is 16.At the same time, except for the first sub stage, the inputs of other sub stages are continuous analog signals.Therefore, the subtraction function and inter stage gain are implemented using the following circuit:

Circuit diagram of subtractor and interstage gain
The circuit relationship satisfies R1=R3 and R2=R4.To achieve inter stage gain, the ratio of R2 to R1 is 16.C1 in the figure shows the stable output of the filtering capacitor.When the Open-loop gain of the operational amplifier is infinite, the closed-loop gain approaches 16.
Finally, this article designs a time-sharing error correction module.Based on the clock signal of the first stage sample and hold circuit, the module samples all the output digital codes in a delayed manner, which ultimately improves the conversion accuracy of Memristor neural network ADC.Because of the particularity of the structure of Memristor neural network ADC, the output needs to be fed back into the synaptic array, so that the neural network can maintain the stability of the energy function, so that the results of Memristor neural network ADC quantification can remain stable.Therefore, in [2], the 8-bit pipeline architecture [2] is: the first level Memristor neural network ADC sub level uses continuous input, the output stage samples, and the output digital code is stable by using D flip-flop to latch.Since the Memristor neural network ADC always has unstable output, when sampling the output, the sampling results still have error code.

2.2.Pipeline sub level comparison
Therefore, this paper illustrates the influence of unstable output of Memristor neural network ADC on dynamic performance through simulation.In Figure 3 based on the pipeline architecture proposed by [2], the output of the first stage is simulated.Based on Simulink, a 4-bit Memristor neural network ADC sub stage is built, in which the input signal of Memristor neural network ADC is a continuous analog signal Vin, and the output signal is a digital code D7D6D5D4.The ideal DAC module is used for digital to analog conversion, converting the digital code D7D6D5D4 into an analog voltage Vh1.After getting the analog output Vh1 of DAC, take the output of DAC as the input of the sampling module, and get Vh2 through the sample and hold module.Finally, the dynamic performance of 4 bit Memristor neural network ADC is measured and calculated through the ADC AC Measurement module, where the input of AC Measurement is Vh2.In Figure 4, a sine signal with a frequency of 100 MHz as the input signal, and displays 16 quantization stages within one signal cycle.Since the Memristor neural network ADC only performs analog-to-digital conversion for the positive level, the DC bias voltage is 0.5 V, the amplitude is 0.5 V, and the amplitude of the overall input signal Vin is 0 to 1 V. Based on the parameters in the table, this article analyzes the output digital code of the first sub level, where the output value Vh1 of the DAC is the analog value corresponding to the continuous digital code.And Vh2 is the analog voltage obtained after sampling Vh1 by the sampling circuit.Due to the sampling frequency of 1.66 GHz, the bandwidth of the operational amplifier needs to be higher than this frequency, set to 4 GHz, and the sampling rate and operational amplifier bandwidth should be consistent with [2].
In Figure 5(a), due to the different conversion times of each bit in sub stage 1, the output waveform of the DAC generates a large number of burrs, and the amplitude of the burrs reaches full scale.The burr signal is the unstable output of Memristor neural network ADC.
In Figure 5 (b), the signal is sampled based on a sampling frequency of 1.66 GHz, representing the analog voltage corresponding to the final digital code D7D6D5D4.As shown in the red box in the figure, the sampled output value Vh2.The waveform error at 3.36 μs, which is due to the sampling circuit sampling the burrs signal.This article takes the input signal Vin=0.5 V as an example to analyze its conversion principle.When the input signal Vin changes from 0.499V to 0.5001V, according to the definition formula of the highest output bit D7 of the Memristor neural network ADC, it can be seen that: Therefore, based on the Danish [2] architecture, this section evaluates the dynamic performance of the first level 4 bit Memristor neural network ADC through the ADC AC Measurement module.

Figure 6 Sublevel Dynamic Performance of Continuous Input
In Figure 6, the input of this module is a digital signal Vh2 and a 1.66 GHz clock signal.The output is a 4-bit sub level dynamic performance, mainly including spurious free dynamic range SFDR, signal-tonoise ratio SNR, and effective conversion accuracy ENOB.According to the configuration mode of sampling module and sampling output in Daniel [2] , the effective conversion accuracy ENOB of 4 bit Memristor neural network ADC is 3.13 bit under the condition of 100 MHz input signal.The reason is that the Memristor neural network ADC takes the continuous signal as the input and samples the digital code at the output, and its output has unstable digital code.After sampling the unstable digital code through the sampling circuit, the quantization process produces error code.

Figure 7 Dynamic performance after error correction
In Figure 7, based on the pipeline architecture shown in Figure 1, this article optimizes the input signals of the first sub level and designs a delay method for the delay error correction module.The input signal Vin adopts falling edge sampling and holding, and the sampled signal is input into the first sub stage.The output signal of the whole Memristor neural network ADC is sampled and output at the rising edge, and the rising edge signal is taken as the output digital code.The error correction delay module delays the sampling clock cycle by half, ensuring the stable quantization of the input signal Vin, and the results are not affected by the burr signal.
Finally, this paper evaluates the dynamic performance of the 4-bit Memristor neural network ADC based on the delay error correction module.Because this paper optimizes the pipeline architecture, considers the unstable state of the Memristor neural network ADC, and conducts delay error correction for the unstable output digital code.Therefore, the effective output bits of the first stage of the pipeline architecture are optimized to 3.96 bits, reducing the impact of burr signals on the Memristor neural network ADC.
In the case of 8 bits, [2] used ideal inter stage parameters to provide SNDR and ENOB in dynamic performance.At a sampling rate of 1.66 GHz, SNDR was 47.5 dB and ENOB was 7.6 bits.In the next simulation, the 8-bit Memristor neural network ADC has a SNDR of 49.31 dB and an ENOB of 7.9 bit at the same sampling rate fs=1.66GHz and input signal frequency fin=700 MHz.Compared to the effective conversion accuracy of 7.6 bits in [2], the advantage of this article mainly comes from the optimization of pipeline architecture.

PERFORMANCE ANALYSIS
In the table I, we analysis the performance of a serious neuronal network ADC.In terms of energy efficiency comparison, since this paper works according to the threshold, and RPU can control the calibration process of Memristor neural network ADC, it can be divided into stable state and unstable state.The steady state power consumption comes from four aspects, including neurons, synapses, DAC and subtractors.Due to the use of MATLAB physical models in this article, discrete devices with similar performance are used for power consumption calculation.The total power consumption of neurons is 2.752 mW, of which the power consumption of operational amplifier LMH6629 (Texas Instruments Inc) is 0.1 mW, and the power consumption of comparator LTC6752-3 (Maxim Inc) is 0.144 mW.A total of 16 operational amplifiers and 8 comparators are required.Due to the use of discrete devices for power consumption calculations, the neuron power consumption calculated in this article is 100 times that of [2] under the same performance requirements.Since the top electrode voltage of the synapse is 0 V and the bottom electrode is the analog voltage 0 or -1 corresponding to the digital code, the power consumption of the synapse is affected by the input signal.The average power consumption of the synapse calculated in this paper is 0.185 mW.The power consumption of the DAC section is calculated based on the discrete device DAC8871 (Texas Instruments Inc), totaling 0.015 mW.The subtractor is calculated based on the power consumption of LMH6629, with a power consumption of approximately 0.1 mW.Therefore, the total power consumption of 8 bit Memristor neural network ADC is 3.052 mW in stable state.
As shown in Table 1, Cao [4] pointed out that FOM in [2] is calculated based on the input signal frequency of 44 kHz, and ENOB is calculated by Oversampling.Thanks to the optimized pipeline architecture in this article, the FOM is calculated based on an input signal frequency of 400 MHz.Therefore, when all Memristor neural network ADCs work at the same sampling frequency, the FOM performance of Memristor neural network ADC in this paper is not as good as that of Memristor neural network ADC in Daniel, but this paper is more consistent with the standard.

CONCLUSION
In conclusion, the proposed 8 bit Memristor neural network ADC can achieve excellent conversion performance, including high sampling rate and high effective resolution.First of all, it enhances the ability of Memristor neural network ADC to regulate the conductance of Memristor through the proposed unsupervised RWC algorithm [5] and the corresponding circuit.Secondly, it effectively suppresses the non ideality of the memristor array and improves the dynamic performance of the Memristor neural network ADC.Finally, by optimizing the pipeline timing, the effective conversion accuracy of the proposed Memristor neural network ADC is further improved.TABLE 1. COMPARISON Cao [3] Cao [4] Danial [1] Danial [2] Our

Figure 1 .
Figure 1.Principle block diagram of pipeline Memristor neural network ADC.It is composed of 4 bit Memristor neural network ADC sub stage, random disturbance unit, sampling and holding module, subtracter, 4 bit DAC and interstage amplifier.

Figure 4 .
Figure 4. ADC sub level simulation circuit using existing pipeline architecture

Figure 5
Figure 5 Comparison before and after sampling.(a) The output value Vh1 of DAC.(b) The output value Vh2 of the sampling circuit.
TABLE OF MEMRISTOR NEURAL NETWORK ADC MLP structure Hopfield structure work