Optimized Voltage Equalization Algorithm for Modular Multilevel Converters

The switching frequency of modular multilevel converters increases with the number of bridge arm submodules. Therefore, an improved voltage equalization technology based on fast sorting algorithm is proposed, which introduces the maximum voltage deviation between sub-modules and reduces the unnecessary switching operations caused by small changes in the capacitor voltage of factor modules. With the help of Matlab/Simulink, a modular multilevel converter with optimized control was simulated to verify the downscaling effect of the voltage-sharing optimization method.


INTRODUCTION
The capacitor voltage imbalance of the submodule can easily cause voltage instability on the DC side and affect the normal operation of the system, so the problem of capacitor-voltage balance control of the submodule has become the focus of research [1,6,9].[1] proposes a voltage equalization control algorithm based on the maximum voltage deviation between sub-modules, which reduces the number of switches, but in some cases, the traditional sorting method is still used, and the number of sorting times and switching frequency cannot be reduced more.In [2], the cardinal sorting algorithm is used to improve the speed of controller calculation of sorting amount, but the spatial complexity of the algorithm is large, and the sorting process occupies a lot of memory.[3] uses the merge sorting method for reducing the number of sorts, but the control process is too complicated, which is not conducive to the design of the controller.[4] proposes to set appropriate threshold limits, group and sort submodules within the allowable range of capacitor voltage changes, and keep the switch in the working state of the previous control cycle as much as possible, but there is no improvement in the sequencing method, and the time complexity is large.[5] uses the characteristics of the prime factor decomposition method and Hill ranking algorithm to the group and sort the capacitor voltages of submodules.The amount of sorting operations in each group is reduced and the voltage equalization speed is improved.However, the voltage between groups cannot be compared and the dynamic performance is poor.[6] introduces a layered container, according to the capacitor voltage, the sub-module is placed in the corresponding container, which can reduce the number of sorts.[8] only changes the traditional sorting algorithm to a fast sorting algorithm.Although the number of sorting can be reduced, the frequency of switching devices cannot be reduced.In [9], the method of double holding factor is introduced to reduce the switching frequency, but the full sorting is still required.In this paper, a voltage-equalization method based on fast sequencing is proposed for the existing capacitor-voltage equalization control theory, and the maximum capacitor voltage fluctuation value is introduced to reduce the frequency of submodule switching.With the help of MATLAB/SIMULINK, the multilevel bi-terminal HVDC transmission system is simulated, and it is verified that the proposed optimized voltage-sharing control method can reduce the frequency of switching devices under the premise of satisfying the stable operation of MMC.

Improvement to the quicksort algorithm
In the case of the same number of submodules, the time complexity of the quicksort algorithm is O (nlogn).The time complexity of the traditional bubbling ranking algorithm is O (n 2 ), it can be seen that the latter is much larger than the former [8,10].Based on the quicksort algorithm, the selection method of pivot elements is changed.Specifically, the mean capacitance-voltage of the submodule is taken as the pivot element.In this way, the length of the subsequence on both sides of the pivot element can be close to each other, and the quicksort algorithm can be avoided by degenerating into the traditional bubble sort algorithm.Next, the minimum capacitor voltage is taken as the pivot element of the smaller side subsequence, and the subsequence is divided into the subsequence that is less than the minimum voltage value and the subsequence that is within the allowable voltage range.For the larger subsequence on the other side, the maximum capacitor voltage is taken as the pivot element and divided into the subsequence within the allowable voltage range and the subsequence which is greater than the maximum voltage value.Finally, the four subsequences are combined and the number of input submodules is determined according to the nearest-level approximation principle.In the next step, all input submodules have the same capacitance-voltage change, and the formula for voltage change is as follows: Therefore, the capacitor voltage is still orderly inside the input and excision groups.At the next sampling moment, a new ordered sequence is obtained by swapping some of the submodules in the input group that has exceeded the limit with the submodules being not in the removal group.Compared with the traditional sorting algorithm, the optimization sorting method has the advantages of avoiding the complete sorting of the capacitor voltage of all the submodules, reducing the amount of sorting calculation and reducing the design cost of the controller.

Improved quicksort pressure balancing optimization strategy
To reduce the switching frequency of submodules, the maximum voltage deviation between submodules is introduced.Combined with the quicksort algorithm, an equilibrium optimization strategy based on the quicksort algorithm is proposed [11] .U cmax and U cmin are the maximum and minimum allowable capacitance voltages of submodules in the bridge arm when the MMC output voltage waveform meets the requirements [2,4] .In this paper, ∆U cmax = 0.1 U c .
The improved voltage balancing optimization process is described as follows.Taking the above bridge arm as an example, in the last control cycle, the number of input submodules of the bridge arm is n past .
(1) When the bridge arm current is greater than 0, the submodule capacitor is charged and the submodule capacitor voltage is sorted from smallest to largest.The input of the pre-n past submodule is denoted as input group N [1, n past ], and the rest as an excised group is denoted as N [n past +1, n].In the next control cycle, the number of input submodules is recorded as n new , and the submodule input difference is ∆n = n new -n past .Considering the relationship between the submodule capacitor voltage and the maximum capacitor voltage U cmax , when ∆n > 0, it needs to add ∆n submodule input.In this case, the input group N [1, n past ] is divided into two subsequences with the maximum capacitor voltage U cmax as the pivot element.The submodules whose capacitor voltage is less than the maximum capacitor voltage U cmax are still placed in the original order to the left of the pivot element, denoted as N [1, p 1 -1].The sequence that is larger than the maximum capacitor voltage U cmax is removed, and the number of removed submodules is n past -p 1 + 1 (where p 1 is the address returned by the pivot element through the counting program); By selecting the pre-∆n+n past -p 1 +1 submodule input of group N [n past +1, n], when ∆n < 0, the last-∆n submodule is cut out for group N [1, n past ].The remaining submodules retain the operation state of the previous step.
(2) When the bridge arm current is less than 0, the submodule capacitor discharges and the submodule capacitor voltage are ordered from largest to smallest.The input of the pre-n past submodule is denoted as input group N [1, n past ], and the rest as an excised group is denoted as N [n past +1, n].The relationship between the capacitance-voltage of submodules and the minimum capacitance-voltage U cmin is considered.When ∆n > 0, it needs to add ∆n submodule.In this case, the input group N [1, n past ] is divided into two subsequences by using the minimum capacitor voltage U cmin as the pivot element.The submodules whose capacitor voltage is greater than the minimum capacitor voltage U cmin are still placed at the address on the left side of the pivot element in the original order, denoted as N [1, p 1 -1].The sequence less than the minimum capacitance-voltage U cmin is cut out, and the number of removed submodules is n past -p 1 +1 (where p 1 is the address returned by the pivot element through the counting program) to select the pre-∆n+n past -p 1 +1 submodule input of N [n past +1, n].When ∆n < 0, the last ∆n submodules are excised.The remaining submodules retain the operation state of the previous step.
The divide-and-conquer method is used to optimize the algorithm and reduce the number of comparisons required by the algorithm in the process of sorting operation [3,5,7].

Simulation verification
The two voltage equalization algorithms are simulated in Matlab/Simulink, the system parameters are as follows.The rated DC voltage is 200 V.The Level number is 5.The inductance of the bridge arm is 5.5 mh.The Energy storage capacitance is 2200 μF.The resistance of the load is 10 ohms.The load inductance is 15 mh.The simulation results verify the effectiveness of the MMC capacitor voltage equalization optimization method.
Figure 1 shows the capacitance-voltage waveform of submodules in the traditional voltage equalization algorithm.Figure 2 shows the capacitance-voltage waveform of submodules when the voltage balancing algorithm is optimized.By comparison, the capacitance-voltage changes of the submodules are consistent under the bubble sorting voltage equalization algorithm.The optimized voltage equalization algorithm is slightly deficient in controlling voltage changes, but the capacitancevoltage of each submodule is still stable around the average 50 V.It indicates that the submodules have a good voltage-balancing effect.Figures 3 and 4 show the output voltage waveform of the two voltage equalization methods.By comparison, it can be concluded that the waveform of the two sorting algorithms under the modulation mode of NLM is almost the same.Therefore, the fluctuation of capacitor voltage within the allowable range will not affect the output characteristics of the MMC.Through the analysis of Figures 5 and 6, it is proved that the switching frequency of the optimized pressure balancing algorithm based on improved quicksort is much less than that based on bubble sort.Therefore, it can be concluded that the optimized voltage equalizing control algorithm based on improved quicksort can significantly reduce the average operating frequency of MMC and reduce the operating cost of MMC on the premise of not affecting the characteristics of output voltage, which proves the effectiveness of the algorithm proposed in this paper.

Conclusion
In this paper, in the analysis of the MMC voltage balancing optimization algorithm, the quick sorting algorithm is improved, and the maximum allowable capacitance-voltage fluctuation value is introduced.Within the allowable capacitance-voltage fluctuation range, the sub-modules are arranged in groups so that the switching device can maintain the maximum working state of the previous step.This method reduces the number of capacitor voltage sorting and the working frequency of the switching device.

Figure 1 .
Figure 1.The Sub-module capacitance-voltage waveform of the traditional sequencing method

Figure 2 .Figure 3 .
Figure 2. The Sub-module capacitance-voltage waveform of the improved control method