Design of Active Closed-loop Driver Chip for SiC

The SiC active control scheme mainly uses phased control, which makes the circuit implementation complex and unfavorable to design due to the need for detection circuits. And the longer feedback delay will affect the accuracy of the control. In this paper, a closed-loop driving SiC scheme is proposed. By integrating the driver circuit, protection circuit, and detection circuit on one chip, the SiC drive current is controlled by a staged control scheme, which can reduce the switching loss with low current and voltage overcharge. The specific circuit design uses Hua Hong BCD350GE technology, which mainly includes a power supply module, a feedback signal processing module, an Undervoltage protection module, a desaturation protection module, a logic control module, and a driver output module, and is verified by beat virtuoso simulation. Test results show that compared with Infineon driver chip 1EDS20I12SV, the switching loss of SiC is reduced by 25.75% when driving SiC at the same turn-off voltage, and the loss reduction is more obvious.


INTRODUCTION
The drive technology can be divided into passive drive and active drive [1].Passive drive mainly relies on changing the size of the passive device to control the gate characteristics, thus controlling the switching characteristics.This scheme is called Conventional Gate Driver (CGD).However, it leads to long switching delays and large switching losses.By studying the relationship between SiC switching characteristics and gate drive, foreign scholars have proposed an active drive scheme to optimize the trade-off between current-voltage overshoot and switching losses during SiC switching.The active drive is based on a closed-loop control scheme.This generally divides the SiC switching process into a delay phase, a current rise or fall phase, and a voltage rise or fall phase by adjusting the variable gate resistance or gate drive current or gate drive voltage [2].By real-time detection of dI/dt, dV/dt or V GE , and V CE during the SiC switching process, the specific switching stage of the SiC is judged and the adjustable amount is changed through the internal logic operation of the chip to realize the phased control.The advantage of this control scheme is that it can better optimize the compromise between current-voltage overshoot and switching loss in the switching process of SiC.The disadvantage is that it increases the detection circuit, which makes the circuit implementation more complicated, and the delay in the feedback circuit will affect the control accuracy, resulting in untimely closed-loop feedback, which affects the optimization effect of this control scheme.This paper proposes a design scheme that integrates the driver circuit, protection circuit, and detection circuit on a single chip.This scheme can reduce the space occupied in the circuit design, reduce the feedback delay, and better optimize the compromise between current-voltage overshoot and switching loss in the SiC switching process [3].
The main work of this paper is to design a SiC closed-loop driver chip with a protection circuit based on the Hua Hong BCD350GE process.This driver chip adopts a closed-loop control scheme.By detecting the dI C /dt and dV CE /dt signals during the switching process in real-time, the specific switching stage of the SiC can be judged and the output current of the driver chip can be adjusted in time [4].In this way, the SiC switching process can be controlled in stages and the switching characteristics can be optimized to achieve a better compromise between current, voltage overshoot, and switching losses during the SiC switching process.In addition, the chip provides Undervoltage protection and desaturation protection for the SiC.When the chip output drive voltage is too low, the chip output will be pulled low and the SiC will be forcibly shut down for protection purposes [5].When the SiC is desaturated, the voltage at both ends will rise to the bus voltage and the chip uses soft shutdown technology to quickly shut down the SiC for protection purposes.

OVERALL DESIGN OF DRIVER CHIP
Based on the specific functional requirements of the SiC device driver chip, this chapter proposes the design of the SiC closed-loop driver chip and gives the overall architecture, including the implementation of the driver chip phased control of the SIC switching process, and Undervoltage protection and desaturation protection functions, analyzes its working principle, and briefly introduces the functions of each submodule [6].

Overall architecture scheme
The chip design described in this paper should include a power module, logic control circuit, drive output circuit, dI C /dt and dV CE /dt feedback signal processing circuit [7], Undervoltage protection circuit, and desaturation protection circuit, as shown in Figure 1.

Phased control implementation
The chip described in this paper is realized by closed-loop feedback control of variable grid current.The specific structure is shown in Figure 2. Controls of the grid drive current circuit in stages by the driver chip

Driver chip protection function
For SiC modules, many fault conditions can lead to damage, such as Undervoltage, short circuit, overcurrent, high dI/dt, dV/dt [8].For the driver chip, implementing the corresponding protection functions for all the above conditions would lead to an overly complex circuit, so we consider the cost and the most likely fault conditions in the application.Undervoltage detection and desaturation detection are used in the fault detection section, which can provide Undervoltage lockout and short circuit protection measures for SiC modules [9].In the chip design described in this paper, the SiC gate drive voltage is the same as the chip supply voltage VCC when it is stable.Therefore, a direct detection of the chip supply voltage is used to determine whether the SiC is operating under voltage.The circuit is shown in Figure 3. Undervoltage module circuit Generally, SiC devices can only withstand such short circuits for 10 us, so the chip protection function needs to completely shut down the SiC within 10 us after the fault occurs to avoid damaging the SiC device and related application circuits [10].In addition, due to the excessive current flowing through the SiC, the fast shutdown speed can cause large voltage spikes and damage the SiC.Therefore, it is necessary to use the "soft shutdown" technique, which is implemented as shown in Figure 4.

OVERALL SIMULATION OF DRIVER CHIP
In this chapter, each submodule is combined into a complete drive circuit, and the simulation verification is carried out.The simulation results are analyzed and summarized in detail.The chip is based on the design and simulation of HuaHong BCD350GE, and the flow plate verification also adopts this process.Subsequently, Altium Designer15 was used to draw the test board, as shown in Figure 6.As shown in Figure 8 (a), when PWM jumps to a high level, the maximum charging current is 2.47 A. When the feedback is triggered, the output current drops to 0. The closed-loop feedback delay during the turn-on process is 15.85 ns.When the feedback is withdrawn, the output current of the chip returns to normal.As shown in Figure 8 (b), when PWM jumps to a low level, the maximum discharge current is 2.49 A. When the feedback is triggered, the output current drops to 0, and the closed-loop feedback delay during the shutdown process is 13.13 ns.When the feedback exits, the output current of the chip returns to normal, meeting the circuit design requirements.
The simulation waveform of the low voltage protection function is shown in Figure 9.At t 1 , the Undervoltage protection is triggered, U VLO_logic jumps to a high level, chip output is always low, and the SiC is kept in the off state.In this case, the V CC Undervoltage threshold is 20.45 V. Since the V E connected to the SiC emitter terminal is 9 V, the SiC grid voltage Undervoltage threshold is 11.45 V.At t 2 , the Undervoltage protection exits and U VLO_logic jumps to a low level.At this time, the V CC recovery voltage is 22 V, that is, the SiC grid voltage recovery threshold is 13 V, meeting the design requirements.
The simulation waveform of the desaturation protection function is shown in Figure 10.

SIC driver chip desaturation protection function simulation waveform
At t 1 , SiC is switched on, and desaturation detection is started at this time.After 3.1 us, the voltage on DESAT_cap exceeds the set threshold, triggering desaturation.DESAT signal jumps to a high level, enters the first stage of the soft shutdown, and starts discharging at a small current of about 70 mA.After 3.81 us, at time t 3 , the Chip output OUT pin voltage is lower than the set threshold value of 2.3 V, DESAT_fast jumps to a high level, enters the second stage of the soft shutdown, discharges with a large current, and quickly pulls down the output pin voltage.Before the RESET signal positive pulse arrives, the desaturation protection signal is locked at a high level and the output remains at a low level.At t 4 , the RESET signal has a positive pulse, the latch is lifted, and the chip begins to enter the next detection cycle.The simulation waveform shows that the circuit meets the design requirements.

Chip output function test
As shown in Figure 11 (a), channel 1 is the control signal, which is generated by the development board and is subject to the reference ground on the development board; channel 2 is the voltage at the chip output port; channel V E is the reference ground; and channel 3 is current at the chip output port.As can be seen from the figure, the PWM control signal of 0~5 V is converted by the chip to the output signal of -9 V~15 V.The signal transmission delay is about 40 ns, and the chip output functions normally.In Figure 11 (b), channel 1 is the voltage of the chip output port, channel 3 is the current of the chip output port, and the maximum value of the output forward charging current is 1.98 A. In Figure 11 (c), channel 1 is the voltage of the chip output port, and channel 3 is the current of the chip output port.The maximum value of the output reverse discharge current is 2.44 A. There is a large deviation between the maximum forward charging current and the design value of 2.5 A. Considering the large size of the output PMOS tube, the influence of the internal parasitic parameters of the chip, and the influence of the parasitic parameters of the external circuit, the maximum output current can not reach 2.5 A.

Chip protection function test
When the chip supply voltage is sufficient, the output is normal, as shown in Figure 11 (a).Using V E as a reference, we slowly decrease V CC .When V CC is below 11.7 V, the chip triggers Undervoltage protection and the output is reduced to -9V, then slowly increasing V CC .The threshold width of Undervoltage protection is 0.9 V.The Undervoltage protection function works properly.
The desaturation protection function is verified, and the test waveform is shown in Figure 12.The indirect 100 pF C blank capacitor of DESAT_cap and V E , the load capacitor, is 10 nF.VE is the reference ground, channel 1 is the chip output port voltage, and channel 3 is the chip output port current, as can be seen from the figure.From the chip output forward charging current to trigger desaturation, it takes 3.8 us.The first stage "soft shutdown" discharge current is 68 mA.When the voltage at the chip output port drops to -6.3 V, which means VSS+2.7 V, it enters the second stage "soft shutdown" and the high current starts to discharge.The desaturation protection function works properly.In actual use, the value of the C blank capacitor can be reduced appropriately to ensure that the whole desaturation protection process is within 10 us.
Desaturation protection function test verification

Chip closed-loop control function test
The chip closed-loop control function is verified by the "double pulse test" method.The chip power supply V CC and V E is an indirect 15 V power supply, V SS and V E is an indirect 9 V power supply, and DESAT_cap and V E is an indirect 100 pF C blank capacitor.The SIC device tested was Infineon 1, 200 V, and 150 A module FF150R12RT4.We test the closed-loop feedback of the SiC shutdown process.When the SiC is off, the initial discharge current is set to open 7 independent drive modules.When the feedback is triggered, all the drive modules are off, the discharge current is 0, and the bus voltage is 200 V.

CONCLUSION
In this paper, after analyzing the basic structure and electrical characteristics of SiC devices, a closedloop control method is proposed based on the principle of overshooting of current and voltage in the process of turning on and off.By detecting the dI C /dt and dV CE /dt signals, the specific switching stage of the SiC can be judged, thus realizing real-time phased control of the SiC grid drive current.To optimize the compromise between SiC switching losses and current and voltage overshoot, and to address the under-voltage faults and short-circuit faults that are prone to occur during SiC operation, Undervoltage protection, and loss-of-saturation protection is provided in the chip design, and "soft shutdown" mode is used to avoid excessive voltage overshoot when loss-of-saturation occurs to protect the SiC device.
According to the guidance of the overall design plan, the sub-module circuit is designed by using the Hua Hong BCD350GE technology and cadence virtuoso simulation software, and the related performance and parameters are simulated and verified.The overall circuit of the chip was built by using the sub-module circuit, the overall simulation was verified and the layout diagram was drawn.The maximum output current of the chip is 2.5 A, and the closed-loop feedback function, the Undervoltage protection function, and the desaturation protection function all work properly.
After the chip flowchart was completed, a test board was drawn with Altium Designer 15, and then the driver chip was tested.The basic output function worked properly and was able to convert the lowvoltage control signal into a high-voltage control signal capable of driving the SiC with sufficient drive capability.The maximum value of the output charging current is less than the design value due to the influence of parasitic parameters.The Undervoltage protection function of the chip is normal.Its threshold width is 0.9 V, which prevents repeated switching of the Undervoltage protection due to chip supply voltage jitter.The loss of saturation protection function of the chip is normal.The duration of the whole "soft shutdown" is 4.9 us, and the duration of the whole loss of saturation protection is within 10 us, which meets the design requirements.During the SiC shutdown process, the chip's closed-loop control function works normally and can control the SiC gate drive current in real-time according to the design requirements.Compared with Infineon's driver chip 1EDS20I12SV, the voltage overshoot during the SiC turn-off process is the same under the same test conditions.Through the chip designed in this paper, the switching loss of SiC can be reduced by about 25.75%.

Figure 2 .
Figure 2. Controls of the grid drive current circuit in stages by the driver chip

Figure 4 .
Figure 4. Desaturation detection circuit 2.4 Feedback signal processing The feedback signal processing module is responsible for processing the received feedback signals.Its main body is a high-speed comparator that compares the received dI C /dt signal and dV CE /dt signal with the designed threshold voltage, respectively, to determine which stage of the switching process of the SiC is currently transmitting the signal to the logic control module.The gate drive current of the SiC is controlled in real-time.The specific circuit of the comparator is shown in Figure 5 (a), and the bias circuit is shown in Figure 5 (b).

Figure 6 .
Figure 6.Driver chip text board

Figure 7 .Figure 8 .
Figure 7.Overall simulation diagram of the driver chip3.2Chip function simulationWith V SS (GND) as the reference ground, all input signals of the chip logic module are connected to a high level, the output load is connected to a 10 nF capacitor, and the DESAT-cap signal is directly connected to V E to ensure that the desaturation protection is not triggered.The transient simulation waveform of the chip at TT process angle and 27 °C is shown in Figure8, where (a) is the waveform of debug process and (b) is the waveform of the shutdown process.

Figure 9 .
Figure 9. SIC driver chip Undervoltage protection function simulation waveform Figure 11.(a) Input/output waveform diagram; (b)Forward charging current waveform; (c) Reverse discharge current waveform Figure 13.(a) SiC shutdown process closed-loop control test waveform (b) 1EDS20I12SV driver chip driver SIC off the waveform Figure 13 (a) shows the closed-loop control test waveform diagram of the SiC shutdown process.Channel 1 is SiC collector-emitter voltage V CE , channel 2 is gate discharge current I G , and channel 4 is the current I C flowing through SiC.The maximum I C value is 115 A and the maximum V CE value is 293 V.The feedback is normal.Through data processing, it is obtained that the turn-off loss Eoff1 is 3.938 mJ. Figure 13 (b) shows the turn-off waveform of SiC driven by Infineon driver chip 1EDS20I12SV.By adjusting the grid resistance, the voltage peak at SiC turn-off is also 293 V. Through data processing, the SiC turn-off loss Eoff2 of 5.304 mJ at this time can be obtained.Compared with the 1EDS20I12SV open-loop drive SiC, the closed-loop control SiC can reduce the turn-off loss by 25.75%.