A high precision and low power consumption switching capacitor readout circuit

In this paper, a high precision and low power switching capacitor readout circuit for MEMS sensors is proposed. The capacitance readout circuit is realized by using the total difference separation loop structure composed of a switching capacitor charge amplifier. In order to reduce the aggravation of common-mode parasitic capacitance to the input offset error and amplifier gain error in the readout circuit, the input common-mode feedback compensation structure and oversampled successive approximation (OSA) readout technology are introduced. In addition, the circuit adopts a non-overlapping nested clock to reduce charge injection and improve output accuracy. Based on SMIC 0.18 μm CMOS technology, the circuit can recognize 0-0.2 pF capacitance signals and convert them into voltage signals, achieving good linear fitting. When the common-mode parasitic capacitance is 1-16 p, it has good resistance to common-mode parasitic capacitance, and the precision of the capacitor readout circuit is increased by 3.9%. Compared with traditional readout circuits, it has a simple structure and low power consumption.


Introduction
Capacitive sensors are widely used in the fields of touch screens, accelerometers, fingerprint recognition, and speech recognition due to a lot of advantages.With the development of the Internet of Things and other related technologies, capacitive sensors including MEMS have been widely used in wearable devices.At the same time, the CMOS technology and the feature size in MEMS technology are reduced to comply with the trend of MEMS sensors being highly integrated [1].The integration of capacitive sensors in applications such as the Internet of Things and wearable devices requires that the process size of sensors is constantly reduced to the magnitude of microns, which makes the capacitance variation of sensors be reduced to the magnitude of flying with the process size [2] [3].The parasitic charge generated on the large parasitic capacitor can easily interfere with or even engulf the signal charge on the sensor capacitor.When the common-mode parasitic capacitor causes the offset voltage in the amplifier input, the finite operational amplifier will amplify the offset error to form the gain error, which severely limits the signal processing range and accuracy of the capacitor sensor readout circuit [4] [5].The OSA technology can effectively improve amplifier gain error, and inputting common-mode control can improve the ability of the circuit to resist common-mode parasitic capacitance.In addition, a split clock bus layout can be used to avoid differential charge injection to further improve accuracy [6].
The main challenge of current flying-level capacitor readout technology is the contradiction between low power consumption and process evolution.The application background of IoT puts forward the requirement of ultra-low power consumption for capacitor readout circuits [7].Although a variety of proposed open loop solutions such as voltage-controlled readout, charge balance bridge, periodic modulation, and double ramp transform can achieve high precision capacitance readout with low power consumption, they cannot get rid of the high sensitivity to parasitic capacitance [8][9] [10].
In this paper, MEMS capacitive high-precision open-loop readout circuit based on OSA technology is developed.On the basis of low power consumption, common-mode control, and clock control are used to effectively reduce the gain error deterioration caused by the parasitic capacitor to flying-class MEMS capacitor sensor system, thus improving the accuracy.

Circuit based on OSA technology
The structure of the capacitor readout circuit proposed in this paper is shown in Figure 1.C S1 and C S2 are the equivalent capacitors of the two differential sensing units of the MEMS capacitive sensor, C P0 is the parasitic capacitance, and C i is the integral capacitance.The gain of the amplifier cannot be infinite in practical implementation, so the voltage difference between the two input ports of the amplifier is not zero, and the differential charge in the mechanical capacitor is not fully transferred to the integrating capacitor, causing the output voltage to increase as the input bias voltage increases [7].This phenomenon is called gain error deterioration.The input difference at both ends of the amplifier is indicated by ∆V 1/A , then it is proportional to the output difference of the amplifier.
According to the law of conservation of charge A capacitor C C is added to the traditional output circuit structure.All switches in the circuit are controlled by two non-overlapping pulses Φ 1 and Φ 2 .The mechanical capacitance bridge forms a dynamic charge transfer to the integrating capacitance C i .The input sampled charge is first stored in the C C , and on the next cycle, the sampled charge is stored in the capacitor C H and capacitor C C , forming a feedback loop.Because of the existence of the feedback path, the output voltage in the sampling stage is still equal to the output voltage in the previous cycle of the amplifying output stage.And the gain error generated by the output voltage of the first cycle is stored in C C .In Φ 2 , the output voltage is In the next cycle, the capacitor C C will gradually absorb the new gain error, and the final output voltage of the circuit is where σ represents the deterioration factor, and N represents the number of clock cycles.As the number of cycles increases, the gain error will gradually be reduced by the capacitor C C , and the output voltage of the sampled charge conversion will eventually approach the ideal value.The analysis shows that the OSA-CVC conversion rate can be improved by high sampling frequency or the high gain of the operational amplifier.

Input common-mode feedback control circuit
The common-mode feedback (icmfb) control circuit is shown in Figure 2 (a).The common-mode capacitor can absorb the common-mode charge errors of the mechanical capacitors C S1 and C S2 .Because the CMOS process is used to manufacture common-mode capacitors and the MEMS process is used to manufacture mechanical capacitors, the matching between them is poor.Therefore, active common-mode feedback should be used as the active part to absorb the remaining common-mode interference charge, so as to reduce the influence of input common-mode error on the output voltage.

Nested clock design
The interference charge injection caused by clock feedthrough, channel injection and coupling interference is a very important factor restricting the output accuracy for the capacitive readout circuit of the flyway level.Figure 3 (a) shows the switched capacitor readout circuit with common-mode feedback.When the C C is charged or discharged, the amplifier output is plugged into the load, resulting in charge injection.This will cause the accuracy and linearity of OSA-CVC to be seriously damaged.Therefore, as shown in Figure 3 (b), a non-overlapping nested clock signal is used to control the operation of the circuit.Φ 1d will be turned on or off after Φ 1 , which will improve the charge effect and further optimize accuracy.

Simulation Results and Discussions
Linearity is one of the core indexes of the capacitance-to-voltage circuit.As shown in Figure 4, when capacitance is -0.2-0.2 p, the circuit output diagram is at different temperatures and process angles.It can be seen that this design can realize the function of the capacitor to voltage and has good linearity.As shown in Figure 5, when the value of the common-mode parasitic capacitance changes from 1p F to 16p F, the output of the circuit without common-mode control decreases by 25.8 mV from 62.71 mV to 36.91 mV, with a 41% reduction.The output of the icmfb circuit was reduced by 5.8 mV from 66.08 mV to 60.28 mV, with an 8% reduction.By introducing the input common-mode control circuit, the ability of the circuit to resist the common mode parasitic capacitance is improved, thus the input common-mode level is stabilized, and the identification accuracy of the capacitor is improved.
As shown in Figure 6, under ideal conditions, the typical output voltage when recognizing a 200 f capacitor is 66 mV.However, the output voltage of the traditional clock under this operating condition is about 68.7 mV, and the error ratio is about 4% compared with the ideal value.In this paper, the output voltage of the non-overlapping nested clock under this operating condition is about 66.1 mV, and the error ratio is only 0.1%.Therefore, the non-overlapping nested clock improves charge injection resistance and the accuracy of the capacitor readout circuit by 3.9%.

Figure 6. Simulation results of conventional clocks and non-overlapping clocks
In addition, compared with the traditional switched capacitor readout circuit, this circuit can act as a traditional CV module during the Φ 2 phase and can act as S&H during the holding phase Φ 1 .Therefore, the circuit in this paper replaces S&H and AAF as front-end modules, thus eliminating the use of these two modules and meeting the requirement of low power consumption

Conclusion
This paper advances a high precision and low power consumption switching capacitor readout circuit.It is designed to extract and amplify capacitive signals.In this paper, we give up the closed-loop structure and adopt the fully differential loop structure to reduce the overall power consumption of the circuit.Due to the non-ideal characteristics of the process and the limited gain of the actual operational amplifier, the input common-mode bias and gain error of the readout circuit will worsen.The input error of the readout circuit is suppressed by adding the input common-mode feedback structure.On the basis of reducing input error and gain error deterioration, the polyphase nonoverlapping clock can reduce the influence of charge injection and improve the precision of the switching capacitor.
Finally, the capacitor readout circuit achieves the design goal of low power consumption and high precision.

Figure 1 .
Figure 1.Structure of a capacitive readout circuit based on OSA technology

Figure 2 .
Figure 2. (a) The structure of an input common-mode feedback control circuit.(b) Schematic of amplifier A 2

Figure 3 .
Figure 3. (a)Switched capacitor common mode feedback structure (b) Non-overlapping nested clock timing diagram

Figure 4 .Figure 5 .
Figure 4. Linear fit of a switched capacitor readout circuit