A MOSFET subdivision, MOSFET-only subthreshold voltage and current reference for LDO applications

This paper proposes a MOSFET-only voltage and current reference circuit, which can simultaneously provide a 2 V reference voltage and 300 nA reference current. This design is mainly used in a low-power Low-Dropout Regulator (LDO) project, after simulation verification, which works well in LDO applications. The circuit is performed by SMIC.18 CMOS technology and simulation with the Cadence platform, with different threshold voltage MOSFET circuit design. The whole circuit works in the subthreshold area, and the overall circuit consists of the start-up circuit, the current reference circuit, the voltage reference circuit, the MOSFET subdivision circuit, and the current mirror output circuit. The circuit has the characteristics of high precision and low power consumption, with a layout size of only 0.015 mm2. Under a temperature range of -30 to 70 °C and a power voltage of 3.3 V, the simulation and post-simulation temperature coefficients (TC) of the circuit are 5.4 ppm/°C and 19.4 ppm/°C, respectively. The post-simulation output reference voltage at room temperature is 2.0008 V, and the working power voltage within the circuit error range is 3.2 V to 3.4 V. Excluding the current mirror output circuit part of the Current-Quiescent (IQ) being 530 nA, the power consumption is 1.75 μW when the supply voltage is 3.3 V, and the design goal is reached.


Introduction
With the rise of the Internet-of-Things (IoT), portable wearable electronics has gradually become the mainstream of industrial production, and the general wearable devices contain analog-to-digital converter (ADC), sensors, power management, and other modules, which makes the study of these modules of great practical value.The power management module is available in almost all electronic devices, among which LDO has become a research hotspot in the field of power management chips with its advantages of small area, low power consumption, simple structure, and high accuracy [1].The general LDO modules are designed with a reference source circuit inside the chip to provide reference power, and external reference sources will make the cost dramatically increase and will also limit the integrity of the chip, making it very valuable for the research of benchmark reference sources.
This design is based on an LDO project to complete the design goal.Because the accuracy of the reference voltage source and the reference current source will greatly affect the precision of the LDO, and LDO is a low-power consumption module, the reference source circuit needs to have high precision and extremely low power use [2].The project LDO needs a reference voltage supply is 2 V, the general band-gap reference (BGR) circuit is the bipolar-junction-transistor (BJT) structure, and the typical output reference voltage value is 1.2 V [3].In order to reach a non-1.2V output, generally, it will use the current model, with the resistance transformation pressure to be achieved, or with the operation amplifier (OPA) to the purpose, which will make the power expenditure greater and increase the area occupied by the reference source [4][5].If it is necessary to meet conditions such as low power consumption and high output accuracy at the same time, the design difficulty is greatly increased.
Therefore, based on the Cadence simulation platform, this paper proposes a structure that uses only MOSFETs, has low power consumption, operates in the subthreshold region, and contains a new MOSFET subdivision reference circuit with a small occupied positive surface.At the same time adjusting the number and size of the division structure is conducive to regulating the value of the output voltage, as well as the TC of the reference power supply.The current mirror can change the output reference current, which can provide a certain idea for the design of a non-1.2V output base source.

The proposed voltage and current reference circuit
The designed circuit consists of several parts of the start-up, the current reference generation, the voltage reference generation, the MOSFET subdivision circuit, and the current mirror output circuit.The circuit shown in Figure 1 is the overall structure of the design circuit.The device used in the structure is all MOSFET, excluding the problem of the resistance loss matching of the BJT BGR [6], and will make the layout have a much smaller area compared to the usual BGR.All of the MOSFET in the circuit work in the subthreshold area, making the circuits have a lower I Q [7][8], which results in less power consumption of the circuit.

The start-up circuit
The reference source circuit generally needs to start-up circuit to prevent the occurrence of zero current in the circle, to ensure the normal operation of the cycle.The start-up circuit in Figure 1 is made up of M1-M6, among which M1 has a relatively large size.In the initial stage of the start, the power supply charges the MOS capacitor to charge M1, causing the M5 gate voltage to rise and to be turned on.The gate voltages of M2 and MP1 are pulled down, ensuring the normal start of the current reference circuit.M6 forms a small capacitor that increases the start speed of the start circuit.M3 and M4 constitute the current loop.After the circuit is normally launched, the excess charge in the starting circuit will flow to the ground, so that the start circuit closes, reducing the I Q .

The voltage reference circuit
The core part of the voltage reference circuit and the current reference circuit are consistent.As shown in Figure 1 for the PTAT & CTAT generator circuit, the high threshold voltage (HV TH ) NMOS (MT4, MT8) and the low threshed voltage (LV TH ) NMOS (MT1-MT3, MT5-MT7) are sufficient [9], HV TH -NMOS threshold voltage is 800 mV, and LV TH -NMOS threshold voltage is 500 mV.In the voltage reference, MT5 and MT6 constitute the complementary to absolute temperature (CTAT) voltage; MT7 and MT8 constitute the proportional to absolute temperature (PTAT) voltage; in the voltage reference, the value of the source terminal voltage is V CTAT , and MT7 is also the drain voltage value of MT8.V CTAT is as follows: Where the value of ΔVTH is approximately the threshold difference between MT8 and MT7.There is a positive value for ΔVTH, the VT value of MOSFET is a negative value, and the values of VT are derived from the drain current formula in the working in the subthreshold area MOEFET: V T is a parameter value for temperature, and it is also a positive value after taking the derivative with respect to temperature, but A is a negative value, so V CTAT has a negative TC.
The production of PTAT voltage is similar to the production structure of CTAT, consisting of MT5 and MT6, and V PTAT can be expressed as: K 5 is MT5's width-to-length ratio; K 6 is MT6's width-to-length ratio; if K 5 was set to be larger than K 6 , the logarithmic value will be a positive parameter; V T is a positive value for taking the derivative with respect to temperature; η is a negative coefficient; then V PTAT has a positive temperature coefficient.At the same time with CTAT and PTAT voltage, there are: V G5 is the gate voltage of MN5; reasonably setting the voltage value and the size of the MOSFET, you can get a voltage output of V G5 with almost zero TC.

The current reference circuit
The core circuit of the generating part of the current reference is consistent with the voltage reference generating circuit, with a similar principle, the zero-TC voltage obtained by MN3 will be converted to current, and this current will be replicated by the cascode current mirror to provide the other supports and as reference current output.The size of MP1-MP9 is consistent, and the MP10-MP13 is half the size of the MP1 width-to-length ratio.

The MOSFET subdivision circuit
The value of the zero-TC voltage VG5 obtained by this circuit is about 350 mV, and the design target gap is huge, according to which the MOSFET subdivision circuit in Figure 1 is designed.It using the MN5 will get the zero-TC voltage converted into a current with an extremely low-TC, and then through the diode-connected MOSFET as a load to subdivision, the main subdivision of voltage is MB1-MB3, and MB4-MB9 is an auxiliary support through a very small current.Among them, MB4, MB5, MB7, and MB8 are the HVTH-PMOS, and the other is the LVTH-PMOS.Their threshold voltages are separately -690 mV and -430 mV.By changing the value of the auxiliary circuit, MOSFET size can be adjusted Vref output, and due to the difference in VTH, the influence of the TC of the current is also different.be combined with a road to the current and has a certain TC adjustment function to the current.By simulation verification, this load can greatly increase reference circuit TC.

Simulation Results and Discussions
Figure 2 shows the design of the reference circuit under 3.3V power voltage, the temperature ranging from 30 to 70°C, and the output reference voltage (V ref ) with the result of the temperature change for tt process corners.The (a) is the simulation result, the curve is presented as a polishing line, its symmetrical axis is near room temperature, and the output at room temperature is 2.0264 V, which is within the error tolerance with excellent accuracy.Its TC is 5.39 ppm/°C and has an extremely low temperature in non-1.2Vreference sources [10], and the simulation results verify that the circuit has reliability under power voltage of 3.2 to 3.4 V. (b) shows the post-simulation result, where its TC is 19.44 ppm/°C, the output voltage accuracy of the post-simulation is extremely high, and the value of it is 2.0008 V at room temperature.Figure 5 shows the design of the reference circuit layout, its area is only 0.015 mm 2 , which optimized its area in the overall layout of the project, so it has a smaller area, but the performance is stable.

Figure 1 .
Figure 1.The proposed voltage and current reference circuit

Figure 2 .Figure 4
Figure 3 (a) shows the design of the reference circuit under 3.3 V power voltage, the temperature ranging from -30 to 70 °C, and the result of the current IB flowing MP14 drain with the temperature change for tt process corners.The current IB can represent the output of the reference current (Ib).The value of the IB is -147 nA at room temperature, the maximum current difference is only 6.5 nA in the temperature range, and it is completely within the error-allowed range.(b) show its post-simulation result by caliber simulation, in which it can not fully position IB and only position the individual transistor (There are six multiples of MP14), 1/6IB is 25.4 nA at room temperature, and both IB output is 152.4 nA.It approximates the simulation results, but post-simulation has a better TC than the simulation.

Figure 5 .
Figure 5.The layout of the proposed voltage and current reference circuit 4. Conclusion This paper proposed a MOSFET-only, subthreshold, low-power consumption reference voltage and current circuit with SMIC.18CMOS technology, which can provide extremely high accuracy reference voltage 2 V and reference current 300 nA, and a new MOSFET subdivision structure that can improve TC is proposed.The reference circuit output V ref pre-simulation TC is low to 5.39 ppm/°C, and the postsimulation TC is 19.44 ppm/°C with a temperature range of -30 to 70 °C.The operating voltage is 3.2 to 3.4 V, and the highest precision output voltage at room temperature is 2.0008 V at 3.3 V supply voltage.Excluding the current mirror output circuit part of the IQ being 530 nA, the power consumption is 1.75 μW at the supply voltage is 3.3 V.It fully meets the needs of the LDO project and works well in the LDO.And with a layout area of only 0.015 mm 2 , at present, this voltage and current reference circuit as a project module entered the chip tape-out process.