A Sigma-Delta Modulator with Single-Pole Double-Throw Analog Switch

In this paper, a high precision and high energy efficiency discrete-time switching capacitive 3-order Sigma-Delta modulator (SDM) is proposed. The SDM is applied to portable electroencephalograms (EEG) because of its little energy and good performance. The energy efficiency levels of the current mainstream modulator systems are analyzed and compared, and the CIFF modulator architecture which is most conducive to realizing high energy efficiency is selected. The single-loop CIFF structure is selected to give consideration to the accuracy and stability of the circuit. The circuit is implemented in a hierarchical structure, and a single-pole double-throw (SPDT) analog switch is adopted to overcome the difficulty of opening conventional CMOS analog switches at low supply voltages and the increase in threshold voltage Vth of NMOS devices due to the base bias effect. The proposed discrete-time Sigma delta ADC modulator is designed with SMIC 0.18um CMOS technology and achieves an SNDR of 101.6dB under a 1.8V power supply voltage and a signal bandwidth of 2kHz. The power consumption is 520uW and the significant bit (ENOB) is 16.58 bits.


Introduction
In recent years, with the in-depth development of neuroscience research, more and more attention has been paid to the neural signal acquisition circuit used for neural network analysis and artificial intelligence research.At the same time, the miniaturization of signal acquisition equipment and the weakness of neural signals require the sampling circuit to develop in the direction of low current, low power consumption, and low noise [1].The nerve signals are first acquired through the nerve electrodes, then amplified by a signal amplifier in the signal acquisition device.The amplified analog signal is passed through the analog-to-digital converter (ADC), where the signal is digitized for computer processing.
With the rapid development of VLSI, the signal processing speed of integrated circuits has been greatly improved, but its accuracy is limited by various non-ideal factors such as circuit noise and misalignment.[2] Due to its oversampling and noise shaping technology, Sigma-Delta ADC, in the process of signal transmission and conversion, the input signal can be retained, and the noise in the bandwidth can be modulated out of the band.The effective resolution (ENOB) can be up to 16 bits, and the SNDR can be up to 100 dB.Sigma Delta ADC is often used in high-precision situations.Due to the small size of nerve signals, circuit noise has a great impact on weak nerve signals.In this regard, Sigma-Delta ADC is very suitable for the conversion of nerve signals.Sigma-Delta ADC is composed of a Sigma-Delta modulator (SDM) and digital extraction filter.The modulator is the core part of Sigma-Delta ADC.The performance of the SDM circuit directly determines the overall performance of Sigma-Delta ADC.In this paper, on the basis of traditional SDM research, a third-order switching capacitor type SDM is proposed.In addition, the flicker noise and offset voltage generated by the operational amplifier can be modulated to the one, three, and five harmonics of the chopper frequency by chopper stabilization technology [3], and the thermal noise can be eliminated by thermal noise cancellation technology [4].Finally, it can be filtered by the post filter to further improve the precision of SDM.
In contrast to continuous time SDMS, integrators in discrete time SDMS usually use NMOS switches and capacitors to sample and hold signals.Integrators, whose coefficient is determined by the ratio of capacitance, are favored because of their excellent robustness to process and temperature changes.But the traditional NMOS switch gradually enters the cut-off region when the input signal approaches the power supply voltage.In addition, due to the influence of the Substrate-Source voltage Vbs, the threshold voltage Vth of NMOS will increase with the increase of Substrate-Source voltage Vbs, which further aggravates the difficulty of opening NMOS.Therefore, this paper proposes the SDPT switch [5] based on the traditional NMOS switch, which can keep Vbs at zero to reduce the increase of threshold voltage.
The structure of this paper is as follows.Section II describes the architecture and basic principles of SDM.Section III focuses on analyzing the basic principle of single-pole double-throw (SPDT) analog switches and its application in SDM.Section IV presents the SDM simulation results.Section V gives a conclusion of the full text.

The architecture of the proposed 3-order CIFF DSM
The SDM designed in this paper adopts the 3-stage single-bit CIFF architecture, as shown in Figure 1.This architecture only requires a single feedback DAC, which is conducive to physical realization.Compared with SDM architecture with multiple feedback paths, such as CIFB architecture, the output of the first two levels of the integrator only contains the shaped quantization noise and does not contain the signal component.In addition, a feedforward path that feeds the input directly is added to the output of the adder.Since the comparator only judges 1 and -1, in practice that the value only judges whether the amount of charge that has converged before the comparator is positive or negative.According to this property, the accuracy of all levels of coefficients is greatly simplified.And this is the disadvantage of multilevel quantization, because multi-bit quantization must make the charge in the interval unique specific value, otherwise the amplitude error change will cause the comparison error.The signal component contained in the output of the SDM is completely provided by the feedforward path, which reduces the pressure of the third-stage integrator to generate signals.Therefore, the output swing of each stage integrator can be very small, which is very consistent with the conditions of low voltage and low power consumption [6][7].Moreover, the signal transfer function (STF) remains 1 at each frequency, and the SDM noise transfer function (NTF) is as follows: (1)

Switched Capacitor Integrator
Integrators in SDM are realized by switching capacitors and operational amplifiers, as shown in Figure 2. In phase 1, the input signal is collected by the sampling capacitor C1, until phase 1 ends.The sampling capacitor retains the value of the signal when the switch is turned off.This stage is called the stage.In phase 2, the amount of charge on the sampling capacitor will be completely transferred to the integrating capacitor C2 due to the virtual short-ground of the operational amplifier and the absence of any other charge release path [8][9].The process can be expressed by Equation (2).[n] (2) Applying the z transformation to Equation ( 2) can get Equation (3) and Equation ( 4) : The integration process is complete.Through Equations ( 2), (3), and (4), the integration coefficient is determined by the holding capacitor C1 and the integrating capacitor C2.

Analysis of Single-pole double-throw analog switch
As shown in Figure 3, the traditional NMOS analog switch is shown, when the gate-source voltage Vgs is less than the threshold voltage Vth, and NMOS is in the cut-off state.The general approach to solve this problem is to use a PMOS analog switch in parallel with it, so as to form a CMOS complementary switch.
The input signal range can reach VSS-VDD.However, due to the substrate bias effect, when the input signal is near the VDD voltage edge, the threshold voltage of the MOS tube becomes larger, resulting in a larger switch-on-resistance transformation.In addition, the bootstrap switch can be used, but because the bootstrap switch needs to combine capacitance, complex structure, and occupies a lot of areas, it is not suitable for this design.Therefore, considering the compromise, the SDM design chooses the SPDT switch.The working principle of the SPDT switch is introduced next.Figure 5.The architecture of the folded cascode transconductance amplifier.

Analysis of First Opamp
As shown in Figure 5, the operational amplifier used in the first-level integrator is the cascode operational amplifier.Since the operational amplifier is a first-order frame system, it is unnecessary to consider the problem of stability.The extremely high low-frequency gain greatly reduces the offset of zero of NFT, thus mitigating the impact of limited low-frequency gain on SDM performance.The grid-source conductance-gm of the input pair of the operational amplifier is designed to be 200uS to ensure that its bandwidth gm/CL (Where CL is the equivalent load capacitance of the operational amplifier) is greater than 10 times the time constant 1/RC (1/10 of the half sampling period 512ns) [10].Thus, the precise establishment of small signals can be realized.The static current at the input stage is designed to be 40uA to ensure the swing rate when the operational amplifier experiences large voltage changes.Thus, the accurate establishment of a large signal can be realized.Figure 7 shows the Bode diagram simulation results of the operational amplifier.In the simulation under different process corners and temperatures, under the equivalent load of 3.4pF(including the sampling capacitance of the post-stage integrator, the capacitor of the common-mode feedback circuit, and the capacitor of the adder), the low-frequency gain of the operational amplifier reaches nearly 80 dB, the unit gain bandwidth (UGBW) reaches nearly 35 MHz, and the phase margin(PM) is 82°, which reflects the fast response characteristics and good stability.
The overall SDM circuit architecture is shown in Figure 6.The capacitive passive adder module is used.Compared with the active adder composed of operational amplifiers, the structure is simpler, the power consumption is lower, and more importantly, the noise transmitted to the comparator will not be generated.According to the previous analysis, in-band white noise is mainly determined by the capacitance of the first-stage integrator.So the holding capacitance needs to be designed to be large.

Experimental Results
The proposed work has been fabricated in the 180-nm CMOS process technology.The overall power consumption of the SDM circuit is 520 uW.The experimental PSD is shown in Figure 8, which displays the PSD results of the SPDT switch modulator and modeling and simulation under Simulink within the signal test range of 2kHz.The input signal is a sine wave.Its frequency is 625 Hz and its amplitude is -9.8dBFS.The sampling frequency is 1024kHz which Oversampling rate(OSR=256).It is obvious that quantization noise has a third-order shaping effect after a fast Fourier transform(FFT) of 163840 points is performed on the digital output results of SDM.Under these conditions, the SNDR and ENOB of the SDM with SPDT switch reach 101.6 dB and 16.58 Bit, respectively.

Conclusion
In this paper, a third-order SDM circuit in the form of a switch capacitance integrator is proposed with an SPDT switch.Some non-ideal factors affecting the performance of SDM are analyzed, such as the noise of each module in the actual circuit, the noise proportion, the finite gain of the operational amplifier, etc.For the low supply voltage of 1.8V, the output swing of the integrator must not be too large, as mentioned in Section 2, so the CIFF architecture is a good choice.At the same time, SPDT is used to overcome the difficulty of opening the traditional NMOS switch under low power supply voltage and the increase of threshold voltage Vth of NMOS devices since the Substrate-Source voltage Vbs is not zero.
Considering that the stability of the loop and the finite gain of the operational amplifier will lead to the harmonic wave of the integrator, which will lead to the deviation of zero of NTF, the cascode operational amplifier is selected.The SDM with SPDT-switch circuit consumes 520uW and achieves an SNDR of 101.6 dB in the bandwidth of 2kHz.

Figure 1 .
Figure 1.The architecture of the proposed third-order SDM.

Figure 2 .
Figure 2. (a) Architecture of the Switched capacitor integrator and (b) its signal timing diagram.

Figure 3 .
Figure 3. (a)Vth of NMOS-Switch and SPDT-Switch according to Vin; (b) Ron of NMOS-Switch and SPDT-Switch according to Vin.

Figure 4
Figure 4 shows the actual circuit diagram of the SPDT switch.During phase 1, MN1-5 and MP1 are switched on and MN0 and MP0 are switched off.MN1 and MP1 form complementary CMOS switches, which are the main on-off switches.As Mn2-5 is switched on and MN0 and MP0 are turned off, the substrate voltage of MN1 and MP1 is VIN, so there is no threshold voltage increase caused by the substrate bias effect.During phase 2, MN1-5 and MP1 are off and MN0 and MP0 are on.Then the complementary CMOS switch formed by MN1 and MP1 is turned off.Moreover, due to the conduction of MN0 and MP0, the substrate voltages of MN1 and MP1 are VSS and VDD, respectively, which further enhances the turn-off effect.

Figure 4 .
Figure 4.The architecture of the SPDT-Switch.Figure5.The architecture of the folded cascode transconductance amplifier.

Figure 6 .
Figure 6.The architecture of the proposed third-order SDM circuit.

Figure 7 .
Figure 7. Bode diagram simulation results of the adopted OTA at different temperatures and process corners.

Figure 8 .
Figure 8. Simulated PSD results of proposed third-order SDM.