Optimal Design of Electromagnetic Tomography Flaw Detection System for Train Wheel Based on FPGA

Electromagnetic tomography (EMT) is a new type of nondestructive testing technology that can be used for metal flaw detection. The implementation of the signal demodulation and filtering algorithm of the current electromagnetic tomography flaw detection system relies on the microprocessor MCU, and the reliability is low in real time. To improve the reliability and system integration of signal processing and transmission of the electromagnetic tomography flaw detection system, this paper uses the field programmable gate array chip to integrate the excitation signal generation module and the digital demodulation module based on the EMT train wheel flaw detection system. A digital filter is designed, and the filter parameters are adjusted to achieve a signal-to-noise ratio of 15 dB. UDP communication protocol is utilized to realize Ethernet communication between FPGA and upper computer. Using three algorithms on the host computer for image reconstruction, the train wheel defect information is visualized. The experimental results show that the FPGA chip improves the immunity of the train wheel flaw detection system, realizes the high integration of the system, and achieves the purpose of train wheel defect detection.


Introduction
For some metal parts of trains, non-destructive testing techniques are usually divided into eddy current testing (EC) [1] , magnetic particle testing (MT), and ultrasonic testing (UT) [2] .At present, the most commonly used method for detecting defects in train components in railways is ultrasonic flaw detection.
Electromagnetic tomography (EMT) is a process tomography technology [3] , which has the characteristics of non-contact, non-intervention, and radiation-free, and can be applied to the nondestructive testing of train metal parts.
This paper is based on the EMT train wheel flaw detection experimental system, with the FPGA chip as the core, which realizes the signal generation [4] , filtering, and digital demodulation functions, and transmits the demodulated data to the host computer through Ethernet communication for image reconstruction.Using FPGA chips to integrate multiple modules, the integration of the system is greatly improved, and the size of the system is largely reduced; FIR digital filter and digital demodulation module inside FPGA are designed to improve the anti-interference and reliability of the system.

EMT system introduction
Electromagnetic tomography based on the principle of electromagnetic induction [5] can reflect the distribution of conductive and magnetic substances in the measured area through image reconstruction.The electromagnetic field physical model of EMT satisfies the following Maxwell equations [7] : In the equation: ω is excitation frequency; B is the magnetic induction; H is the magnetic field strength; E is the electric field intensity;  is the permittivity.In the EMT system, when the excitation frequency is low, the influence of the displacement current can be ignored, that is  0 ( 2 ) The magnetic vector is , which satisfied: Putting  into Eq.( 1): In the equation:  represents the current density of the coil.The induced voltage value  detected in the coil can be expressed as: In the equation: φ is the magnetic flux through the coil;  indicates the number of turns of the coil;  indicates the area of the coil;  indicates the length of the coil;  is time;  / is the rate of change of the coil magnetic flux.
From Eq. (4) and Eq. ( 5), it can be seen that conductive or magnetic substances will change the distribution of the magnetic field in the EMT system.
EMT systems generally include sensor coil arrays, signal conditioning modules, data acquisition modules, and image reconstruction computers, as shown in Figure 1.

DDS algorithms
The sinusoidal excitation signal required in the DDS [6] module synthesis system and the basic principle are shown in Figure 3.It is composed of a phase accumulator and waveform memory.In the figure,  represents the address bit width of the lookup table, and _ is the frequency control word.The frequency control word controls the stepping of each phase and then controls the frequency of the signal.The obtained sinusoidal output  can be calculated according to the system clock , and the sinusoidal output frequency is: Figure 3. Principle of the DDS algorithm In addition to generating system excitation signals, the sine and cosine digital sequences synthesized by DDS are used as demodulation reference signals.

Digital Demodulation Design
The digital demodulation module demodulates the excitation current and induced voltage signals, and the digital quadrature sequence demodulation method is used to demodulate the excitation current signal and the induced voltage signal.
Detection signal s n , In-phase reference signal r n , and Quadrature Reference Signals q n are: In the equation,  indicates the amplitude of the sampled signal;  indicates phase offset;  indicates the number of sampling points.It must meet the periodic sampling conditions: In the equation,  is a constant,  indicates the sampling frequency, and  indicates the frequency of the sampled signal.The in-phase and quadrature components are expressed as: The amplitude of the detection signal can be expressed as: After the demodulation is completed, the data is transferred to the communication module, and the next demodulation is automatically started.

Filter Module Design
We design the FIR digital filter inside the FPGA and use the FIR IP core to directly generate digital filters.The COE file required for the FIR IP core is generated through the Filter Designer tool in Matlab, and the parameters of the filter are adjusted in Filter Designer.The sampling rate is set to 32MHz, which is consistent with the sampling frequency in FPGA.We change the order of the filter and compress the bandwidth to improve the signal-to-noise ratio (  ).The excitation signal frequency of this system is 100 KHz, and the cut-off frequency is set to 150 KHz.The signal before and after filtering is analyzed in the frequency domain in Matlab, as shown in Figure 4.The signal-to-noise ratio is an important indicator of filter, and its calculation formula is: In the equation: is the target signal power, is the noise signal power.By changing the order of the FIR digital filter from 1-20, we calculate the relationship between the SNR and the order.The relationship between the order and the SNR is shown in Figure 5.As the filter order increases, the SNR increases.When the order increases to a certain range, the system performance does not improve significantly.Finally, the order of the FIR filter is determined to be 16, After filtering, and the signalto-noise ratio reaches 15dB, which meets the system requirements.

Upper and lower computer communication
The FPGA communicates with the upper computer through Ethernet and transmits the demodulated data to the upper computer.Based on UDP transmission, we formulate the communication protocol: the upper computer sends an inquiry command, as Table 1.The Sampling rate, the program is set to 50M 4 Cached data length When acquiring data, the host computer sends a control command requesting data, and the development board sends data, as illustrated in Table 3 and Table 4 1024 Data information We configure the LWIP protocol stack through SDK program development, use the DHCP protocol to assign IP addresses, and set the memory of the packet buffer (pbuf).Functions are written to implement UDP initialization, receive callbacks, answer host computer commands, and send data functions.The workflow of upper and lower computer communication is shown in Figure 6.7 is a physical diagram of the system, which is verified by electromagnetic tomography experiments in the train wheel flaw detection experimental system [7] .The excitation signal of this system is 100 KHz.After the collected data is filtered and digitally demodulated in the FPGA, it is transmitted to the host computer through Ethernet communication.Finally, the LBP algorithm, Tikhonov regularization algorithm, and Land Weber [8] iterative method are used for imaging on the host computer.The imaging results are shown in Table 5: (3) Both rim and tread are defective It can be seen from the physical picture of the system that the use of an FPGA chip reduces the volume of the EMT flaw detection system.From Table 1, it can be seen that the image reconstruction results obtained from the experiment can reflect the position and size information of the wheel defect, Land Weber algorithm has better imaging results than other algorithms.The experiment shows that after using the FPGA chip to integrate multiple modules of the EMT train wheel flaw detection system, the system works normally and completes the image reconstruction of the train wheel defect.The experimental results prove the feasibility of using FPGA chips to replace some modules of the EMT system.The use of FPGA chips can improve the reliability of system signal demodulation and filtering modules, enhance system integration greatly, as well as optimize system performance.

Conclusion
To improve the performance of the EMT system, this paper is based on the FPGA chip, which integrates the signal generation module, digital demodulation module, filter module, and communication module of the traditional EMT system.The electromagnetic tomography experiment verification is carried out through the train wheel flaw detection experimental platform, and three imaging algorithms are used in the host computer for image reconstruction to realize the defect detection of train wheels.The experiment proves that using FPGA chips to replace some modules in the EMT flaw detection system can effectively reduce the volume of the system and improve the integration and system performance of the EMT system.
Three different imaging algorithms are used in the host computer for image reconstruction, and the imaging results are compared to determine the best imaging method for train wheel defects and realize train wheel defect detection.
FPGA internal resource layout structure characteristics and calculation mode make it difficult to implement more complex electromagnetic tomography image reconstruction algorithms.Using the high-performance soft core integrated into the FPGA chip, the image reconstruction algorithm can be

Figure 1 .
Figure 1.EMT system structure diagram3.Design of FPGA internal modulesIn this paper, an FPGA chip is used to integrate the DDS module, digital demodulation module, filter module, and communication module of the EMT system.The internal logic of FPGA is shown in Figure2.

Figure 5 .
Figure 5. Signal-to-noise ratio curve of the filter

Figure
Figure7is a physical diagram of the system, which is verified by electromagnetic tomography experiments in the train wheel flaw detection experimental system[7] .The excitation signal of this system is 100 KHz.After the collected data is filtered and digitally demodulated in the FPGA, it is transmitted to the host computer through Ethernet communication.Finally, the LBP algorithm, Tikhonov regularization algorithm, and Land Weber[8] iterative method are used for imaging on the host computer.The imaging results are shown in Table5:

Table 1 .
Query command The development board sends a 27byte response command through Ethernet, which includes the board MAC and IP address, effective data length, sampling rate, and buffer data length, as shown in

Table 3 .
. Control commands (sent by the host computer)

Table 4 .
Reply commands (sent by the development board)

Table 5 .
Comparison table of experimental results