Test Method of Secure and Controllable FPGA Chip Used in Flexible DC Transmission Control and Protection System

Flexible DC transmission control and protection system is a high-performance distributed computing system, which has the characteristics of high-speed data acquisition and fast processing, and uses a large number of high-performance FPGA (Field Programmable Logic Array) chips. FPGA has the characteristics of high integration and complex manufacturing process, and its security and controllability is faced with many challenges. The reliability of FPGA is an important standard to measure its performance, so reliability test fault screening is very important to ensure its normal operation. Although the automatic test equipment (ATE) can test the fault of FPGA, it is not convenient for field testing due to the price, test environment and other factors. In this paper, a design scheme of built-in self-test (BIST) for fault detection and fault diagnosis is proposed, which can detect faults of look-up table (LUT) and interconnection resources (wires and programmable switches). At the same time, considering the effect of rising temperature on fault probability, a controlled self-heating element (SHE) is constructed by using the internal resources of FPGA to provide the required temperature for BIST testing. Finally, an integrated layout scheme of BIST and SHE is proposed. An experiment of self-heating of FPGA chip is completed by TSINGHUA PGL22G, which verifies the correctness and feasibility of the theory.


Introduction
In the context of constructing a new power system based on new energy, flexible DC transmission technology will play a key role in enhancing system support capacity, achieving long-distance transmission of clean energy from remote areas, friendly absorption of isolated new energy such as offshore wind power, broad optimization of energy resource allocation, promoting the realization of the dual carbon goals.China has built and put into operation the world's highest voltage level and largest capacity flexible DC transmission project.
The flexible DC transmission project has a large transmission capacity, and its faults can greatly impact the AC system.Therefore, the stability, reliability, real-time, and high-speed performance of the control and protection equipment are of great importance.The system uses a large number of high-speed operation chips, but almost all of the core chips used are imported, and the technology is heavily depended on foreign sources.Therefore, it is urgent to prepare for the risk of imported chip and technology supply disruption, and carry out research on the national production substitution of chips for the flexible DC transmission control and protection system.This will break foreign technology monopolies and comprehensively improve the degree of independence of the system, effectively ensuring the power security of China.
FPGA chips are the most widely used chips in the flexible DC transmission control and protection system and have the characteristics of high computational speed, low power consumption, and flexible configuration.The security and controllability of FPGA chips is crucial for improving the degree of independence of flexible DC transmission and promoting the development of important fields such as the power system.This has important strategic significance.
FPGA is a regular structure that consists of a set of logic modules, which are internally connected through wires and interconnect switches.By programming the logic modules and interconnect structure, specific functions and interconnect paths can be implemented, thus achieving the overall functionality [1]   .FPGA can realize various hardware circuit functions, so by fully utilizing its reprogrammability, many application programs can be developed.It also has the advantages of high execution efficiency and strong parallel computing capability, and is easy to be upgraded [2] .Different FPGA chips use different processes, such as EG4X20BG uses 55 nm process, and PGL22G uses a more advanced 40 nm process.Advanced processes improve integration while also bring many reliability challenges, such as heat dissipation, increased circuit noise sensitivity, and transient and permanent failure issues [3][4] .
The localization of FPGA not only needs to address issues such as manufacturing process brought by advanced process technology, but also needs to ensure the correctness and stability of its functionality throughout its lifecycle through continuous testing.This includes both fault testing during production and fault testing during post-production use [5] .
The testing methods for FPGA can be divided into two categories.First, Automatic Test Equipment (ATE) is used to perform fault testing on the FPGA [6][7].Second, the advantage of FPGA's programmability is used and utilizing internal logic units are utilized to perform fault testing through the Built-In Self-Test (BIST) method [8] .Fault testing using ATE has standardized testing procedures, a simple process, and strong portability and versatility, but it also has the disadvantage of expensive equipment.In addition, with an increasing number of computational units inside the FPGA and a limited number of I/O ports, it becomes increasingly difficult to test the internal resources of the FPGA by using ATE equipment.Furthermore, dedicated ATE equipment is not convenient for testing FPGAs used in the field.
The BIST approach is to program different logic units within the FPGA as the Test Pattern Generation (TPG), Block Under Test (BUT), and Output Response Analyzer (ORA).During testing, the TPG generates test vectors that are sent to the BUT, which sends the computed results to the ORA for analysis to check if the BUT unit is functioning properly [9] .After testing, the TPG, BUT, and ORA are reconfigured and swapped to traverse all logic units.Therefore, the BIST method does not require additional hardware and is convenient for later testing.
With the development of FPGA testing technology, BIST technology has also received attention.However, a significant amount of research work has assumed that only Configurable Logic Blocks (CLBs) may fail, while in testing schemes for interconnect resources, it is assumed that CLBs have no faults [10] .These testing schemes test CLBs and interconnect resources separately, assuming that other functions are normal when testing one function without treating FPGA resources as an organic whole.
Step-by-step testing leads to an increase in the number of FPGA programming, an increase in testing time, and a higher probability of repetitive testing of the same resources, which is not conducive to improving testing efficiency [11][12] .
Due to the increased probability of faults with the temperature rise of FPGA chips, the stability of FPGA chips under high-temperature conditions is also an important part of chip function testing.Thermal awareness testing is commonly used to check such faults and ensure that the chip quality meets the requirements.This testing scheme often uses external devices such as a thermal chamber or oven to heat the chip to a certain temperature and then conduct testing.However, for the FPGA chip testing in flexible DC transmission control protection, the external heating devices are often bulky and expensive and are not suitable for on-site testing.Moreover, high temperatures may have an impact on other components or solder joints on the PCB board.
Therefore, this paper first proposes a testing method that integrates CLBs and interconnect resources, combining the characteristics of each testing phase and fully utilizing the internal resources of the FPGA.This optimizes the traditional step-by-step testing method, which has problems such as long testing time, high programming frequency, and high testing repetition rate.Then, to address the shortcomings of traditional thermal awareness testing, a self-heating testing scheme for FPGA is proposed.Finally, the self-heating scheme and the improved BIST scheme are integrated into the same FPGA to achieve the above two testing processes.The proposed testing scheme does not require any external devices which reduces the testing cost and will not affect other components on the PCB board.Since each FPGA works independently during the testing process, it can perform large-scale simultaneous testing in the flexible DC transmission control protection system, greatly reducing the testing time.Moreover, this method can be used not only for testing in the production and manufacturing process but also for user acceptance and periodic testing in the later stages.The proposed heating scheme was verified on the Ziguang PGL22G system board and integrated with the proposed BIST scheme.

Overview of the principle of self-testing of secure and controllable FPGA chips for flexible DC control and protection systems
Flexible DC transmission systems require high dynamic response capabilities, so it is necessary to use high-performance processors to achieve fast logic calculations and closed-loop control functions.Largecapacity FPGAs are also needed to develop high-speed backplane buses that can implement multiprocessor parallel computing and high-speed interfaces with valve control systems.Core chips used in flexible DC protection system platforms mainly include main controllers (CPUs), digital signal processors (DSPs), programmable logic devices (FPGAs), analog-to-digital converters (ADCs), network chips (COMs), and storage chips (FLASH), among others.Taking a certain DC project in China as an example, the number of protection system devices is around 50 -60, with more than 4,000 various types of circuit boards, and the usage of major chips exceeds 30,000, almost all are imported from the abroad.Among them, the number of FPGA chips is huge and is the core component that ensures the high-speed operation of the protection system.Against the background of FPGA localization, the security and controllability of FPGAs is of paramount importance for the localization process, breaking foreign technological monopolies, and ensuring the security of national power system.
Due to the fact that controllable FPGA chips, especially controllable high-performance FPGA chips, are still in the early stages of production and manufacturing, ensuring their product reliability and stability is particularly important.Although ATE equipment can be used for testing in the production and manufacturing process, it is especially important to research convenient self-testing methods for the practical use of controllable FPGA chips, especially in usage scenarios where large quantities of localized FPGA chips are required, such as in the case of flexible DC control and protection systems with high computational performance requirements.Therefore, it is necessary to focus on researching self-testing methods for FPGA chips.

FPGA architecture
The FPGA is composed of an n n  CLB array and local/global interconnect units, as shown in Figure 1.The CLB is the programmable functional core of the FPGA and capable of performing logic operations.The CLB consists of a look-up table (LUT), a multiplexer (MUX), and a D-type flip-flop (DFF).The multi-inputs (I1, I2, etc.) can realize any logical function through the LUT, and the output is a signal O1.The input signal C directly controls the MUX or DFF to control the output of the CLB.
The local interconnect unit is connected to the CLB and includes wires and connection modules.The connection module includes a programmable interconnect point programmable switch (PIP-PS) and a programmable multiplexer switch (MUX-PS).The local interconnect unit transfers signals into and out of the CLB. Figure 2 (a) shows a schematic diagram of the PIP-PS, which is represented by a square pattern and includes a transistor and an SRAM unit that can be programmed to turn on or off the transistor.Figure 2   The global interconnect unit is composed of a switch matrix (SM).The wires and programmable cross-point switches (PCP-PS) of the SM form horizontal and vertical signal channels connecting CLBs.The SM is connected to k wires on each side.The PCP-PS, shown in Figure 2 (c), is represented by a diamond shape within the SM.It consists of six PIP-PS that can be programmed to connect wires in six directions (east, west, south, north, up, or down).

BIST fault detection principle
This article proposes a BIST (Built-In Self-Test) strategy that configures 22 CLBs as a test group, as shown in Figure 3.In each test group, 4 CLBs are configured as TPGs (Test Pattern Generators) to generate test vectors, and 6 CLBs are configured as ORAs (Output Response Analyzers) to compare with each output of the BUT (Being Under Test) and check the test results.The remaining 12 CLBs and their corresponding local/global interconnect units are used as BUT and tested in sequence.The test process can be described as follows: first, the test group is generated in the FPGA, and then the initial test configuration is loaded to form a predetermined circuit with the local/global interconnect units and CLBs.Next, the TPG is configured to generate test vectors to be sent to the BUT.Finally, the ORA analyzes the output results of the BUT to detect and diagnose faults under this configuration.After this stage is completed, the FPGA is reconfigured, and the CLBs serving as TPG, BUT, and ORA are rotated until all CLBs have been tested as BUT.To comprehensively check all the above-mentioned faults in a sequential order, the testing of each BUT is carried out according to the following approach.As shown in Figure 3, one wire (bold line) is used to detect open-circuit faults in the global interconnect, five wires (gray lines) are used to detect fixed on/off faults in the local interconnect and fixed 0/1 faults in the CLB, and programming can be used to detect delay faults in the PUT.The remaining eight wires (dashed lines) are used to detect shortcircuit faults in the global interconnect.After one round of testing is completed, these 14 wires are reconfigured.
The proposed BIST scheme also uses CLBs in FPGA to implement TPG and ORA to reduce additional hardware testing costs.The TPG in Figure 4 is an address generator composed of 10 MUXs, 10 LUTs, and 10 DFFs, which is used to generate corresponding test patterns by continuously generating addresses in LUTs.The input-output relationships of LUT1LUT5 and LUT6LUT10 in Figure 4 are determined by Equation (1).The 10 LUT units can choose any expression in Equation (1), where " * " represents logical negation, and "*" represents any variable.For example, LUT1 in Figure 4 is labeled as C1, which means that when the input of LUT1 is the value corresponding to "Address [5:1]", the output is the value corresponding to C1.For example, when "Address [5:1] = 10000", the output C1 of LUT1 is "1".If the outputs of LUT1 -LUT5 are "11101", a test vector "11101" can be generated when triggering the DFF.
In Figure 4, the two-input XOR gate and the four-input OR gate in ORA are used to test for open and short circuit faults in the global interconnect, and the five-input parity checker is used to detect faults in LUTs and local interconnects.The parity checker consists of a five-input XOR gate and a unit clock delay, and is implemented by using internal logic gates and CLB DFFs.In addition, the (Pass/Fail) checker in the ORA circuit is used to trigger the fault propagation circuit, which transfers faults from the output of the BUT to the fault dictionary used for fault diagnosis, as shown in Figure 4.The ORA judgment logic is as follows: [5], [4], [3], [2], [1], where   is the output of the parity checker.

BIST fault detection process and fault diagnosis principle
The fault detection process is as follows: (1) Detection process for global interconnect open faults.The TPG signal is set to "1" and connected to one of the BUT outputs through an XOR gate.If the output of the XOR gate is "1", a fault has occurred.
(2) Global interconnection short circuit fault.In the ORA circuit, the outputs of 8 BUTs are connected to an OR gate.When the outputs of the BUTs are set to "00000000", if there is a short circuit between a specific wire and any of the BUT outputs, the OR gate will output "1".
(3) The detection process for local interconnect stuck-at fault and LUT stuck-at 0/1 fault is as follows.The 8 output paths of the 8 LUTs in the BUT are connected to the 5-input XOR gate in the ORA circuit.The XOR gate detects if any of the output paths of the LUTs are stuck at 0 or 1.Additionally, the local interconnect wires connected to the LUT inputs and outputs are also connected to the XOR gate.If any of these wires are stuck at a fixed logic level, the XOR gate will detect the fault and output a "1" signal, which is then latched by the DFF in the ORA circuit.
(4) Delay faults.To detect delay faults, a loop is formed by returning the PUT to the CLB.The falling (or rising) edges are detected and the fault is indicated through the parity checker.
To diagnose the faults, it is necessary to locate the faulty LUT and record its fault type.The former can be achieved by observing the output signals of ORA, and the latter requires comparing the output of BUT with the fault dictionary to obtain.The fault dictionary records each of the above-mentioned faults.When the control circuit is opened by ORA's fault signal "1", the signal from the faulty BUT is stored in a register.[ The fault diagnosis process is described as follows.
Global/Local Interconnect Testing; The schematic diagram for fault detection in global/local interconnect is shown in Figure 5.All inputs of the LUT in BUT are connected to interconnect line 1 (LUT in PGL22G has 5-bit inputs), and the outputs of LUT1 to LUT8 are connected to interconnect lines 2 to 9 respectively with the input-output relationship set to Equation (1).Table 1 lists the input test signals for three types of interconnect faults, as well as the corresponding output without faults and the fault output.The test signal "10 0000 0000 0000" is generated by the TPG circuit, and the output without faults is shown in Table 1 as "11 1111 1110 0000".
Fault 1, the global interconnect open circuit; In Figure 5, if there is an open circuit (marked as F1 open) between the input of LUT1 and the input of LUT2 on wire 1, the output of wire 1 will be "0", and the inputs of LUT2 to LUT8 will change from "11111" to "00000", and the outputs of wires 3 to 9 will also become "0".Table 1 lists the results under this fault, and abnormal values (underlined and bold) can be observed from wires 1, 3 to 9.

Global open circuit
Global short circuit Fault 2 , the global interconnect short circuit; Under normal circumstances, the values of wires 1 -9 are "1".If wires 10 -14 are short-circuited with the above wires, the fault can be detected by checking the values of the wires.For example, if wire 1 and 10 are short-circuited, wire 10 will become "1".
Fault 3, the local interconnect MUX-PS open circuit fault; If there is an open circuit between input 3 of LUT1 and wire 1, the input of LUT1 will change from "11111" to "11011", and the signal on wire 2 will change from "1" to "0".Fault 4, the PUT delay fault; Figure 6 shows an example of PUT falling edge detection, assuming the initial values of Q1 and Q2 are both 1.By observing the changes in Q1, we can detect whether there is a delay in the PUT.When the input changes from 0 to 1, in normal operation, Q1 should change from 1 to 0 and then back to 1, but if there is a fault, Q1 will change from 1 to 0 and remain at 0. Therefore, if there is a PUT delay fault, the output on wire 2 will change from 1 to 0. Fault 5, the LUT stuck-at-0/1 fault; Figure 7 is the test circuit for LUT stuck-at-0/1 fault.To detect the fault of a single LUT, the input-output relationship of the LUT is set to C8 in Equation (1).When the TPG generates signals of "01 0000 0000 0000" and "11 1110 0000 0000", the normal output should be "01 0001 1111 1110" and "11 1110 0000 0000" respectively.
If LUT1 has a fixed 0 fault, the output of wire 6 will change from "1" to "0", that is, when the input of LUT1 is "01 0000 0000 0000", the output will be "01 0000 1111 1110".However, it is not possible to detect the fixed 1 fault of LUT1 by using the input signal "01 0000 0000 0000", because the signal on wire 6 is "1" regardless of whether the fault exists or not.Therefore, the input signal "11 1110 0000 0000" is selected for testing.If there is a fault, the output signal will change to "11 1111 0000 0000", and wire 6 will show that LUT1 has a fixed 1 fault.The test results of the two cases are shown in Table 2.

Wire
Input Without fault Fixed 0 Input Without fault Fixed 1 According to the description of the fault diagnosis process above, by comparing the output fault signals with the fault dictionary of different test items, the fault type and location can be determined.For example, "01 0000 0000 0000", "11 1111 1111 0000", "10 1111 1110 0000", "01 0000 11111110", "11 1111 0000 0000" correspond to the global open circuit fault in F1 (as shown in Figure 5), wire 10 short circuit fault, MUX-PS open circuit fault in F1, LUT1 fixed 0 fault, and LUT1 fixed 1 fault. [4] [5] [4]  The basic circuit diagram for implementing heating is shown in Figure 8, which consists of a ring oscillator and a controller that control the switching rate.This circuit can be implemented by using LUTs.The feedback signal from the output of the LUT to its input is switched rapidly by a switch network, which increases switch losses and generates more heat.For multi-input LUTs, the feedback signal can be connected to all input ports to generate the maximum power dissipation.In actual operation, to prevent the feedback signal from being optimized by software, the various signals can be connected to the MUX in the CLB.
To reduce the proportion of the control unit and maximize power consumption, each SHE includes a control unit and multiple LUTs for oscillation, as shown in Figure 9.The working logic of the LUT is shown in Figure 10, which is an extension of the oscillation circuit in Figure 8.The feedback inputs of the other three LUTs in the same CLB are also used as inputs of this LUT, which can further increase the amount of heat generated.The control unit is shown in Figure 11, and its "serial output" signal is sent to the "control input" ports of all LUTs inside the SHE.The DFF is used as a shift register to store a clock cycle of the control signal "serial input"."Set 1" forces synchronization by outputting "1".An SHE can contain many LUT units, however, the more LUTs there are, the more complex the wiring becomes.Additionally, all LUTs in an SHE must work or stop at the same time.If there are too many LUTs in an SHE, it is not convenient for fine control of the FPGA temperature.Therefore, it is advisable to choose a small number of LUTs to form an SHE, such as no more than 10.Each SHE occupies a small space, making it easy to interleave with BIST structures.To simplify the control of SHE and reduce its occupation of FPGA resources, multiple SHEs' inputs and outputs can be connected in a chain, forming a self-heating chain (SHC), as shown in Figure 12.The number of SHEs in the SHC can be adjusted freely, providing great flexibility.With this connection method, a single signal "heating control" can be used to change the number of SHEs in the SHC that are in working state, thereby adjusting the heating generated by the SHC. Figure 14 shows the timing diagram of SHEs in an SHC containing 6 SHEs after the RESET signal is initiated.To change the heating generated by the SHC, the duty cycle of the "heating control" signal can be adjusted to open or close each SHE.For example, to activate half of the SHEs, the duty cycle of "heating control" needs to be set to 0.5, as shown in Figure 13, with three SHEs working in each clock cycle.

SHE
To perform BIST on an FPGA, a specific configuration file needs to be set up based on the requirements.To generate a uniform thermal distribution across the entire FPGA, the number of SHEs can be adjusted, which can be done gradually during the initial heating process where all SHEs are activated.When the temperature reaches a certain level, the number of SHEs is slowly and linearly reduced until a uniform thermal distribution is achieved.The relationship between the number of SHEs and the desired maximum temperature depends on the FPGA used, so the FPGA can be pre-calibrated to determine this relationship.The calibration process involves testing different numbers of SHEs with different distributions and observing the temperature results by using a thermal imaging camera.After calibration, this information can be used to design a pre-defined heating control unit, which starts/stops a portion of the SHEs based on the desired maximum temperature.

Combination of SHE and BIST for FPGA test method
The structure of SHE proposed in this article is very flexible for integration with BIST.The connection of LUTs inside SHE allows for free distribution, leaving space for BIST placement around SHE.The integration of SHE and BIST structures can be chosen to include only SHE configuration during the first configuration, utilizing all FPGA resources to quickly heat up to the desired temperature.After that, a parallel testing scheme is used to integrate SHE and BIST, where SHE's role is to maintain temperature and reduce the demand for logical resources.In this parallel testing scheme, SHE and BIST structures are integrated into each testing configuration, by adding SHE to the basis of TPG, BUT, and ORA in BIST structure.This scheme can achieve precise temperature control and reduce the number of required reconfigurations.The two structures designed after integration are shown in Figure 14.
Figure 14 illustrates a test layout of BIST integrated with SHE where each rectangular box represents a Configurable Logic Module (CLM) unit (i.e., CLB as mentioned previously) in PGL22G, with 24 CLMs included in the example.The four small rectangular boxes represent four 5-input LUT units where 14 LUTs in TPG are used to change the voltage levels on 14-wire, and every two CLMs in BUT send signals to ORA for detecting the normal operation of CLMs.One LUT in SHE serves as the control unit, and the remaining 9 LUTs serve as oscillating heating units.It can be seen that BUT occupies half of the CLM units, while the other half is configured as TPG, ORA, and SHE.In the next configuration, a swap is performed so that all CLMs are tested as BUT.

Experimental verification
The main functions proposed in this paper for the FPGA include self-testing and self-heating.Selftesting is mainly focused on theoretical explanation, which can be easily verified through logical analysis.However, the feasibility of self-heating theory and the ability to heat the FPGA quickly enough to meet on-site testing needs requires experimental verification.To validate the effectiveness of SHE in heating up the FPGA, the code was written based on the theoretical analysis presented earlier, and the temperature changes of the FPGA were observed by using a thermal imaging camera.To confirm that the wiring structure of the SHE unit conformed to the theoretical expectation after the code was compiled, the same method was used to write the code on the Vivado software platform (which has higher visualization capabilities than the PGL22G PDS).After programming the FPGA and running the code, the chip temperature was observed by using a thermal imager, as shown in Figure 16.It can be seen that the temperature of the FPGA gradually increased from 57.4℃ to 69.6℃, and then to 96.7℃.It is worth noting that due to the heat dissipation effect of the package shell and the copper on the PCB board, the core temperature of the FPGA exceeds the temperature of the package shell.In order to obtain a more accurate temperature distribution and peak temperature, the package shell of the FPGA can be removed during pre-calibration testing.After obtaining the heating scheme, it can be used for on-site testing of the same type of FPGA without removing the package shell and using thermal imaging.It can be seen that the self-heating scheme can raise the core temperature of the FPGA to nearly 100 degrees, so it is suitable for on-site BIST of the FPGA.

Conclusion
To perform on-site testing of secure and controllable FPGAs to ensure their normal operation throughout their lifecycle, this paper proposes a self-heating element (SHE) and built-in self-test (BIST) scheme that can use internal FPGA resources for self-heating, thereby creating more rigorous test conditions that can be controlled to increase the core temperature to the set value.Through experiments, the use of the self-heating scheme heated the UNIS PGL22G chip to 96.7℃, verifying the feasibility of the selfheating scheme.Therefore, through the research in this paper, by integrating SHE and BIST into the same FPGA testing scheme, it is possible to simultaneously detect whether all LUTs and interconnect resources inside the chip are functioning properly, and the testing process requires no additional hardware, making it suitable for regular testing of field-used FPGAs.
(b) shows a schematic diagram of the MUX-PS, which is represented by a group of triangles on a horizontal or vertical wire and selects the conduction path through configuration bits during the configuration phase.

Figure 3 .Figure 4 .
Figure 3. Diagram of the functional configuration of the conductor.Common faults in FPGA can be classified into four categories: open/short faults, stuck-at faults, fixed 0/1 faults, and delay faults.Open/short faults occur on the PCP-PS or interconnects of the global interconnect, while stuck-at faults appear in the transistors of the PIP-PS and MUX-PS of the local interconnect, fixed 0/1 faults occur in the LUT of CLB, and delay faults require specialized testing paths (Path Under Test, PUT) to be detected.
is the output of the BUT, 0 _ 1 t b  and 0 _ t b represent the first input and output of the BUT, and _ 5 xor b

Figure 8 .Figure 9 .Figure 10 .
Figure 7. LUT fixed fault detection.Figure8.Oscillation heat generation basic circuit.3.Built-in self-heating principleThe SHE proposed in this article mainly uses the LUT and D flip-flops in the CLB.Since the CLBs are evenly distributed in the FPGA, it is possible to freely choose which locations to heat up to achieve the desired temperature distribution.Therefore, controlling the heat generation of the CLBs is an ideal choice for self-heating of the FPGA.

Figure 14 .
Figure 14.BIST test layout with integrated SHE.

Figure 15 .
Figure 15.Basic logic unit in PDS.
Figure 16.FPGA temperature distribution under thermal imager.
To verify the self-heating function, the UNIS PGL22G was used as the test platform.The basic logic unit of the PGL22G FPGA is the CLM, which is similar to the conventional CLB definition.There are two types of CLMs, which are CLMA and CLMS.Both consist of 45-input LUTs, selectors, and triggers.CLMS supports all the functions of CLMA and adds support for distributed RAM.The schematic diagram of both types in the UNIS FPGA development software Pango Design Suite (PDS) is shown in Figure15where FY represents LUT, L represents selector, and FF represents D trigger.