An LDO without a Capacitor Required in Applications

Linear voltage regulator with low voltage dropout is widely used in DC/DC circuits because of the advantages of simple structure, low noise, high efficiency, and small package size. In this paper, high stability LDO linear voltage regulator with low static current is designed. By using a voltage detection module, the pass transistor in the regulator can be quickly regulated or switched on and off under load transient conditions. In addition, the stability of the LDO is improved by using an NMOS pass transistor and diode clamp architecture. The test results show that the typical values of linear adjustment and load adjustment of the voltage regulator are 20 mV and 200 mV, respectively. The maximum output current is 60 mA, the load current is 20 mA, and the output pressure difference under 4.8 V output voltage is 210 mV. Compared with traditional LDO, although the output current is not the maximum, the difference and stability of output pressure are greatly improved.


Introduction LDO (Low Dropout Regulator
) is widely used in DC/DC circuits, which is a portable product due to its outstanding advantages of simple structure, low noise, high efficiency, and small package size [1] .As the integration technology becomes more mature, the integration degree is higher and higher, and the power consumption is also increasing, which requires the power supply to have a very high conversion efficiency.The power conversion rate of LDO is defined as: where I out is the output current, V out is the output voltage, I q is the static working current, and V in is the input voltage.To improve conversion efficiency, the values of input-output differential pressure V out and static current I q must be reduced.The typical LDO static current ranges from 40 to 100 µA, and the differential pressure ranges from 200 to 400 V.In addition, stability is also the key index of LDO.The traditional LDO uses ESR (Equivalent Series Resistance) on the output capacitor to generate the zero point and the pole on the adjusting tube grid to cancel each other to make the system stable.However, ESR is easily affected by the environment, such as temperature, and the output current is limited to a small range.Given the above problems, this paper designs the band gap reference that generates the low-temperature drift reference current as the bias of LDO, which achieves the purpose of reducing the static current and improving the conversion efficiency [2] .protection.The band gap LDO provides a stable, high-precision, and the low-temperature coefficient reference voltage.Undervoltage locking is to disconnect the circuit when the voltage is lower than the reference voltage, to protect the circuit and reduce consumption.Overtemperature protection in the environment temperature is too high, the system heat dissipation is poor, and the load current is too large, which leads to the rise of transistor temperature.The use of three-tube voltage and temperature negative correlation protects the circuit and prevents the high temperature from burning the transistor.The traditional LDO is an error amplifier that compares the output feedback voltage V FB with the reference voltage V ref and amplifies the difference to control the ongoing state of the regulating tube, thus obtaining a stable output V out .Its value can be expressed as: LDO provides a stable voltage source for the entire circuit, and it has a high requirement for stability, so it needs to be connected with a large off-chip capacitor at the output end to stabilize the output [3] .This paper proposes to further stabilize the output voltage by the combination of diode and NMOS tube clamp voltage, to achieve the effect of no off-chip capacitor.After the circuit works normally, the MN3 grid voltage is too low and will be turned off.Charging of C1 will make MP2 turn off.At this time, we start the circuit to turn it off and reduce consumption.Q1, Q2, R4, MP18, and MP19 constitute the bandgap reference circuit, among which MP18 and MP19 are regarded as the differential input end of the amplifier, using the amplifier characteristics of a virtual short and virtual break to make the grid voltage of the two transistors equal [4] .The output voltage of bandgap reference cryogenic drift is:

Bandgap reference circuit
The design of the reference circuit in 3.5-5.5V voltage at the temperature of −40-125 ℃ can provide stable 1.18 V reference voltage stable output, and the total circuit consumption current is 20 µA.When the voltage temperature and process change, the output voltage fluctuation remains within 0.17%.The common-mode suppression capability of the differential structure on the input signal is enhanced.MN6, as a second-stage common-source output, provides a large enough output swing.The Miller capacitor C1 pushes the secondary pole to a frequency point greater than the unit-gain bandwidth, and the zeroing resistor R1 pushes the zero far beyond the secondary pole so that it does not affect the gain attenuation rate.In this design, the low-frequency gain is expected to be 80 dB and the phase margin is to be 63° [5] .Figure 4 shows the design structure of the adjusting tube, which provides two guarantees for the stability of LDO.First, MN7 is combined with voltage regulator D3 to stabilize the grid voltage of MN7 at 6 V [6] .The second is that the error amplifier will compare the reference voltage with the reference voltage to control the switch of the regulator MP8.The MP8 adopts a high-voltage tube with a large size.The advantage is that the voltage value is high, and the regulator can be protected from breakdown when the power supply voltage is too high [7] .The Block is a voltage detection module.As the input voltage increases, the high and low levels are output, the regulating tube module is controlled to start quickly, and the output voltage is raised to supply power to the bandgap reference circuit.

The design structure of the transmission tube
Figure 5 shows the design structure of the voltage detection module.Q1, Q2, and R13 form a simple bandgap structure.With the increase of input voltage at the clamp, Q1 has a larger current amplification factor than Q2 due to its emission junction area which is 3 times that of Q2, and MP11, MP12, and MP14 form current mirrors.The pull-up current Ip generated by the leakage stage of MP12 is greater than the pull-down current Id generated by Q2, so the pull-up voltage is generated by the gate of MP13.MP13 is turned off to make the plo output low, start the adjustment tube, and raise the output voltage of LDO [8] .When the pull-up current Ip is equal to the pull-down current Id, the output is reversed, and the currents flowing through Q1 and Q2 are equal, then: 13 The expression of I Q1 can be calculated in Formulas 4 and 5 as follows: 1 13 ln 3 Thus, the flipping voltage V clamp expression is: According to the principle of band gap base low-temperature coefficient, R13, and R14 can be adjusted for the temperature coefficient of V clamp , to reduce the influence of temperature on the tube starting circuit.In addition, MN12 and R12 form a hysteresis loop to avoid starting the circuit when the voltage is not stable and stops working and to protect the transistor from being damaged.Figure 6 shows the relationship between the band gap reference voltage and temperature under typical working conditions (vdd=5 V).The measurement range is -40 ℃-150 ℃, the maximum value of the reference output voltage varying with temperature is 1.49 mv, and the temperature coefficient can be calculated as 7.84 ppm/℃.
Figure 7 shows the gain and phase margin of the error amplifier.The low-frequency gain of the amplifier is 76.8 dB, and the phase margin is 59°at a unit gain.Due to the pole splitting of Miller capacitor C1, secondary points are pushed beyond the unit-gain bandwidth, so the stability of the system is not affected.When we debug the zeroing resistance, the zero point is pushed far beyond the unit-gain bandwidth to avoid the gain attenuation rate being affected [9] .The input voltage range of the voltage regulator is 4-10 V, the output voltage is 4-5.5 V, and the maximum value of the output current is 40 mA.When the power supply voltage changes from 8-10 V, the linear transient response shown in Figure 7 is obtained, and the output jump is less than 15 mV.When the load changes in a step from 1 to 20 mA, as shown in Figure 8, the establishment time is less than 70 us, and the output voltage jump is less than 150 mV [10] .As can be seen from Figure 8 and Figure 9, the circuit has excellent stability characteristics.In various transient responses, there is no

Figure 1 .
Figure 1.The design structure of LDO

Figure 2 .Figure 2
Figure 2. The design structure of the bandgap reference Figure 2 is a soft start circuit without static current consumption of the resistance divider bandgap reference circuit.MP2, MP3, MP4, MN3, and C1 constitute the starting circuit.When the en terminal voltage increases, the grid voltage of MP3 and MN3 decreases.While vdd increases, C1 is charged, and the grid voltage of MP2 increases accordingly.When MP2, MP3, and MN3 are all on, the starting circuit starts to work, making the grid voltage of MN5 too high and getting rid of degenerate points.After the circuit works normally, the MN3 grid voltage is too low and will be turned off.Charging of C1 will make MP2 turn off.At this time, we start the circuit to turn it off and reduce consumption.Q1,

Figure 3 .Figure 3
Figure3.The design structure of the error amplifier Figure3shows the design structure of the error amplifier.MN2, MN5, MP5, MP6, and MP4 constitute the classic five-tube differential structure, among which MP5 and MP6 are regarded as the first-stage input differential providing high gain to the tube, and MP4 as the current source providing current to the amplifier.MN3 and MN4 enhance the symmetry of the five-tube differential structure.The common-mode suppression capability of the differential structure on the input signal is enhanced.MN6, as a second-stage common-source output, provides a large enough output swing.The Miller capacitor C1 pushes the secondary pole to a frequency point greater than the unit-gain bandwidth, and the zeroing resistor R1 pushes the zero far beyond the secondary pole so that it does not affect the gain attenuation rate.In this design, the low-frequency gain is expected to be 80 dB and the phase margin is to be 63°[5] .

Figure 4 .
Figure 4. Adjustment of the design structure of the pipe

Figure 5 .
Figure 5.The design structure of the voltage detection module

Figure 6 .
Figure 6.Temperature characteristics of the bandgap reference voltage

Figure 7 .Figure 8 .
Figure 7. Gain and phase margin of the error amplifier