Programmable Synchronous 2-Bit Counter in Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is a newly-developed nanoscale electron device that has the potential to replace the conventional transistor in the future. Owing to the unique field-coupling mechanism of QCA, several constraints must be fulfilled during the design of QCA sequential circuits, which makes the construction of sequential circuits a relatively intractable issue in QCA research. In this paper, a programmable synchronous 2-bit counter in QCA is proposed, which is consisted of combinational logic and falling edge-triggered JK flip-flops. The count mode of the programmable counter can be changed on-demand by mode control signals. Moreover, an initial state setting method of the QCA circuit is also proposed during the design of the counter so that the effects of random initial states can be avoided. Simulation with QCADesigner software demonstrates the validity of the proposed counter.


Introduction
Moore's law, which has guided the evolution of semiconductor products for more than half the century, is nearing its end [1].But the progress of integrated circuit will never stop, huge efforts have been made by researchers to find novel materials and devices which has the potential to stimulate new directions for the future of IC.These new devices such as spintronics [2], carbon nanotube [3], and quantum-dot cellular automata (QCA) [4] could be the possible successors to the conventional siliconbased CMOS technology.QCA is a novel electron device that is based on a coulomb coupling mechanism.Compared with CMOS integrated circuits, QCA circuits have some unique features [5].For instance, in a QCA sequential circuit, the combinational logic is also under the control of clock signals beside the flip-flops.As a result of these unique features of QCA, some constraints must be considered during the design of QCA sequential circuits [6].In concrete terms, all feedback paths from the outputs of flip-flops to their inputs should have identical delays.All state variables should be updated simultaneously.These constraints make the construction of QCA sequential circuits more difficult than the design of QCA combinational circuits, for the existence of feedback paths.So compared with the design of QCA combinational circuits, sequential circuits in QCA draws more attention from researchers in recent years.Taking the QCA counter as an example, 4-bit QCA ring counter [7], 2-bit and 3-bit synchronous counter [8][9][10], and n-bit synchronous counter [11] have been reported so far.However, the count mode of these reported counters is all fixed.Recently, a selective QCA counter which can selectively count the numbers is proposed [12], however, when the count mode changes, the layout of the counter also needs to be changed.That is to say, these QCA counters are not programmable.To the best of our knowledge, a programmable counter in which the count mode can be changed by mode control signals on demand has not been considered by the QCA researchers.In this work, a programmable synchronous 2-bit QCA counter is proposed and validated, it can realize mode 2, 3 and 4 counters according to different mode control signals respectively.An effective approach to set the initial states of the QCA circuit is also proposed so that the effects of random initial states can be avoided.
The frame of this article is as follows.The QCA fundamental knowledge is summarized in Sec. 2. The schematic diagram design of the programmable counter is presented in Sec. 3. In Sec. 4, the construction of the proposed counter using QCA is exhibited.In Sec. 5, the results of the simulation and detailed analysis of the programmable counter are presented.The whole paper is summarized in Sec. 6.

Basics of QCA
QCA is a novel current-less nanoscale electron device.Due to its unique coulomb interaction-based mechanism, QCA has inherent superiorities of very high speed switching and ultralow power dissipation, which make QCA a potential alternative device to build next-generation integrated circuits.As displayed in Figure 1, the polarized states of QCA cells are used as carriers of binary information.When the polarization P = +1 (P= -1), it means logic "1" ("0").Up till now, fundamental QCA components such as binary wire, inverter, majority gate, coplanar crossover and fanout which are basic blocks to design various kinds of QCA circuits are well developed [5], as shown in Figure 1.If one input port of the majority gate is set to P = +1 (P= -1), an OR (AND) logic gate is constructed.What should be paying attention to is that QCA wires are also used as interconnections in a QCA circuit, so metal wires cannot be found in the QCA circuit.The QCA cells can be fabricated by metal quantum dots [13], semiconductor quantum dots [14] or molecular [15].Under the QCA cells layer, the four-phase electric field clock signals are generated by the current flows in the metal wires [16], and all QCA cells in a clock zone are modulated by the identical clock signal.

Circuit diagram design of programmable 2-bit synchronous counter
The states diagram of the synchronous 2-bit programmable counter is displayed in Figure 3.
11, namely a mode 4 counter.The state transfer process is summarized in Table 1.According to the states diagram, the state transfer equations of the programmable 2-bit counter are obtained in Equations ( 1) and (2).   1 1 00 00 00 00 JK flip-flop is chosen as the sequential device of the counter, so the driving equations of the counter are obtained as follows: where J 2 , K 2 and J 1 , K 1 represent the input signals of two JK flip-flops respectively.Depending on Equations ( 3) and ( 4), the schematic diagram of the programmable 2-bit counter is obtained, as displayed in

QCA implementation of programmable 2-bit counter
In our previous research, a falling edge-triggered JK flip-flop [8] was proposed, as displayed in Figure 5. Now it is used to construct the programmable 2-bit counter directly.In Figure 6, the layout of a programmable synchronous 2-bit counter is presented.This layout is designed by using QCADesigner 2.0.3 software [17] which is a recognized simulation tool in the QCA research area.The widths and heights of all the QCA cells in the counter are 18 nm, the diameters of quantum dots in QCA cells are 5 nm, and the center-to-center spacing between QCA cells is 20 nm.CP is another input signal of the counter except for M 2 and M 1 .Figure 6.QCA layout of the programmable 2-bit counter.
The outputs of these two JK flip-flops will only change as the falling edge of the CP signal comes.There is a delay of two clock cycles in the JK flip-flop.Another point that needs to be mentioned is that, in our previous JK flip-flop design, there is an inverter in the K port [8].But in Figure 6, the inverters in the K ports cannot be found because both the two K ports of JK flip-flops receive the output of NAND gates.It is obvious that the inverters can be deleted and the NAND gates can be changed into AND gates, which could contribute to the simplification of the counter layout.The comparative study of the proposed counter and prior reported counters are shown in Table 2.Although the programmable character causes an increase in layout area and delay, the cost is tolerable in specific designs where real-time reconfigurability is required.

Simulation and analysis of programmable 2-bit counter
To demonstrate the validity of the proposed counter, the layout in Figure 6 is simulated based on the bistable approximation engine of QCADesigner 2.0.3.In Table 3, some key simulation parameters are provided.Table 3. Simulation parameters in QCADesigner 2.0.The input signals M 2 and M 1 traverse three clock cycles before arriving at the JK flip-flops, while the feedback paths from the outputs of JK flip-flops to their inputs also traverse three clock cycles.Therefore, this layout design coincides with the constraints of the QCA sequential circuit, for the delay of input signals is equal to the delay of all feedback paths, as shown in Figure 7 (a), when M 2 M 1 = 00, the output Q 2 Q 1 = 00 all the time, it is named Zero Mode here.By using the Zero Mode, the initial states of the counter can be set before it works, so the random initial state problem [8] of the QCA circuit can be solved effectively.It is shown in Figures 7 (b) to (d) that M 2 M 1 = 00 during the first three clock cycles to set the initial states to Q 2 Q 1 = 00.Because the overall delay of the counter is five clock cycles, the valid outputs appear five clock cycles later after the first CP falling edge comes, as shown by the arrows in Figure 7.When M 2 M 1 = 01, it is found in Figure 7 (b) that the count mode is 00→01→00; when M 2 M 1 = 10, it is found in Figure 7 (c) that the count mode is 00→01→10→00; when M 2 M 1 = 11, it is found in Figure 7 (d) that the count mode is 00→01→10→11→00.It is clear that the proposed layout can realize the states diagram in Figure 3 successfully.There is no doubt that if the number of combinational logic circuits and flip-flops is increased, a programmable counter with a larger bit size can be obtained.

Conclusion
In this paper, a programmable 2-bit counter in QCA is proposed, and a detailed analysis of the proposed counter is presented.The count mode of the programmable counter can be changed ondemand by mode control signals.The schematic diagram of the programmable 2-bit counter is obtained on the base of the states diagram, which is made up of 8 fundamental logic gates and 2 JK flip-flops.QCA layout of the counter is designed with the consideration of QCA sequential circuit constraints.Simulation results demonstrated the function of the proposed counter at last.Although the programmable character causes an increase in layout area and delay, it is still attractive for some QCA sequential circuits in which real-time reconfigurability is important.An approach to solve the random initial state problem of the QCA circuit is also provided, which can also be used in the construction of other QCA sequential circuits.If the proposed programmable counter is used in a QCA system instead of a mode fixed counter, there is no doubt that the flexibility of the system will be improved.

Figure 1 .
Figure 1.Fundamental components of QCA.The computation of the QCA circuit is under the modulation of four-phase clock signals[5], which is another unique feature of QCA, as shown in Figure2.When the electric barriers generated by the clock signals change, the barriers between quantum dots in QCA cells are also changed, so the clock signals can modulate the polarization of QCA cells.Different colors are used to represent different clock zones in a QCA layout.Between two adjacent clock zones, the phase difference is π/2.The main purpose of the QCA clock is to power the state switching of cells to synchronize the data and control the data flow direction.The QCA cells can be fabricated by metal quantum dots[13], semiconductor quantum dots[14] or molecular[15].Under the QCA cells layer, the four-phase electric field clock signals are generated by
Q 2 and Q 1 are 2-bit output signals of the counter.There are four output states, namely Q 2 Q 1 = 00, 01, 10 and 11.M 2 and M 1 are 2-bit mode control signals.As shown in Figure 3, when M 2 M 1 = 00, the output hold in the state Q 2 Q 1 = 00 all the time; when M 2 M 1 = 01, the counter has two output states, Q 2 Q 1 = 00 and Q 2 Q 1 = 01, namely a mode 2 counter; when M 2 M 1 = 10, the counter has three output states, Q 2 Q 1 = 00, Q 2 Q 1 = 01 and Q 2 Q 1 = 10, namely a mode 3 counter; when M 2 M 1 = 11, the counter has four output states,

Figure 3 .
Figure 3. States diagram of the programmable 2-bit counter.

Figure 4 .
The counter is made up of 8 fundamental logic gates and 2 JK flip-flops.Simulation results from Multisim 10.0 software, a widely used circuit simulation tool developed by National Instruments Corporation demonstrate that the schematic diagram functions well.

Figure 7 .
the simulation results.In each sub-figure of Figure 7, the first three lines are input signals, namely M 2 , M 1 and CP; the fourth line is Q 2 and the fifth line is Q 1 ; the last line is one of the clock zone signals.Simulation results of the programmable 2-bit counter.(a) Zero Mode, when M 2 M 1 = 00 (b) Mode 2 counter, when M 2 M 1 = 01 (c) Mode 3 counter, when M 2 M 1 = 10 (d) Mode 4 counter, when M 2 M 1 = 11 EEICE-2023 Journal of Physics: Conference Series 2625 (2023) 012011

Table 1 .
State transfer table of the programmable 2-bit counter. n

Table 2 .
Comparison of QCA counter designs.