Automatic Solder Joints Layout Algorithm Based on Electrostatics Model

Currently, there are many automated algorithms for solder joints layout, such as genetic algorithms, ant colony algorithms, and neural network-based algorithms. The goal of these algorithms is to find the best solder joint layout to improve the quality of welding. However, due to the limited space in mobile phones, sandwich boards are widely used, and their structure determines that the number of solder joints should be increased as much as possible to enhance the flexibility of the device layout. This article proposes an automatic solder joint layout algorithm based on the electrostatics model for the solder joint layout problem on PCB frame boards and LGA boards. The solder joint and frame board are mapped as charged bodies. The position of each solder joint is continuously iteratively corrected so that the total potential energy of the system is zero, thereby satisfying the constraints to obtain a reasonable layout of the solder joint and increase the number of solder joint layouts. Experimental results show that this algorithm can achieve the maximum automatic layout of solder joints on PCB frame boards and LGA boards, and the space utilization rate can reach 95.5% of the theoretical maximum value.


Introduction
In smartphone applications, to achieve stronger functionality, the single mainboard has gradually been replaced by a sandwich structure with multiple mainboards.The PCB board and LGA board are in the middle of the sandwich board, and as many solder joints as possible need to be arranged to connect the upper and lower mainboards, as shown in Figure 1.These solder joints need to be spaced a certain distance apart to facilitate subsequent wiring requirements.At the same time, these solder joints distributed on the PCB board and LGA board must be a certain distance away from the edge of the board to meet the physical electrical requirements.In the past, these tasks were completed manually, with low efficiency, and without a guarantee of the maximum number of solder joint arrangements.There is currently no specific research on automatically maximizing the number of solder joints while meeting electrical constraints in the industry.Against this background, this article designs and implements an effective automatic solder joint layout algorithm.
This article discusses the equal-circular packing problem [1] , which involves placing multiple nonoverlapping equal circles inside a closed curve-shaped container to maximize the container's utilization.To solve this problem, both domestic and international scholars have utilized heuristic algorithms [1][2][3][4][5][6] .He et al. [7] introduced a tension model to handle the circular packing problem with static equilibrium constraints and achieve favorable results.In the area of integrated circuit global layout [8] , Lu et al. [9] proposed a global layout method based on electrostatics, which maps the layout instance into an electrostatic system model, uses the simulated electric field force to separate each layout unit, and ultimately arrive at a reasonable layout plan.Cheng et al. [10] further improved upon ePlace, resulting in better solution quality and faster solution speed.Figure 1.PCB frame board solder joint layout By taking inspiration from He Kun's tension model and ePlace/RePlace's electrostatic system model, this paper proposes a new method that uses an electrostatic model to address the automatic solder joint layout problem on PCB frame boards and LGA boards.

Description of the problem
The solder joints layout problem to be investigated in this paper can be summarized as follows: the layout area and constraints are given, such as solder joints size, the minimum distance between solder joints, and the minimum distance between solder joints and area boundaries, to obtain a reasonable layout which can accommodate the largest possible number of solder joints in the layout area.
The problem can be stated as follows: The objective function: ( ) where N is the number of solder joints to be accommodated within the layout area.Constraints include: 1) All solder joints lie inside the polygon layout area A: ( , ) where C is the set of solder joints represented by the center of the circle, and for the solder joint i C  , the coordinates of its center are ( , ) i i x y .For the layout region R, the set 1 2 1 2 { , , , ; , , , } T s s x x x y y y   s of vertices on the boundary is denoted by M and the set of line segments between two adjacent points of the boundary is denoted by B.
2) The distance between one solder joint and another solder joint is greater than or equal to its minimum distanced constraint d , which means that the individual solder joints do not overlap each other: where r is the radius of the solder joint.
3) The distance between the solder joint and the boundary of the layout area is greater than or equal tol, which means the minimum distance constraint between the solder joint and the boundary of the layout area:

Handing of constraints
Regarding constraints 2) and 3), they are handled as follows based on the practical situation of the solder joint layout.
Handling of solder joint spacing As shown in Figure 2, the radius of the solder joint is expanded to 2  , where is the angle between the direction vectors of the line segments 1 B and 2 B , and D is the parallel line spacing.Thereby, the vertices of the layout area can be calculated after the inward or outward expansion.

Algorithm design and implementation
Considering solder joints as charged entities and the boundary of the layout area as a charged container, according to electromagnetism, all solder joints in the layout area will experience an electrostatic force and generate potential energy.Thereby, the electrostatic model can be derived.
We denote the boundaries of the layout area as 0 and denote the solder joints ( {1,2, , }) i as i .The coordinates of the center of the circle of the solder joint ( {1,2, , }) x y d the set of coordinates of the solder joint C is called a layout.
For a given layout, the potential energy ( ) e U X of the system is defined as: The potential energy between the solder joints is inversely proportional to the square of the solder joints spacing and the potential energy between the solder joint and the boundary is inversely proportional to the distance between them.The layout C is a feasible solution only when ( ) 0 e U X  .At this time, solder joints do not overlap each other, and the corresponding arrangement satisfies all the constraints.
According to the current potential energy of each solder joint of the system, we continuously adjust the position of the solder joint.If ( ) 0 e U X  finally, it illustrates that the layout area can accommodate N solder joints; if ( ) 0 e U X  within the number of iterations finally, it means that the layout area can not accommodate N solder joints.
To converge the algorithm faster, the number of solder joints N is initially given a theoretical maximum value overlap N .
where R S is the acreage of the layout area, i C S is the acreage of a single solder joint after constraint processing, and CNT is the space utilization for the densest arrangement of circles (hexagonal lattice), as shown in Figure 4.However, the space utilization of the solution obtained after satisfying all the constraints is much smaller than the theoretical maximum in practice, due to the limitation of the layout area boundary.solder joints in the layout area, and calculate whether the total potential energy ( ) e U X of the system is 0. If it is 0, it means that the layout area can accommodate this number of solder joints, thus the maximum number of solder joints that can be accommodated can be determined by the dichotomy method; if it is not 0, it means that there is an overlap between the solder joints in the system.So we give each solder joint a displacement in the direction of the potential energy gradient according to the potential energy distribution.The displacement size is determined by the number of iterations and the magnitude of the force on the solder joints in the electrostatic model.At the same time, we give the system a random perturbation to avoid the algorithm falling into a local optimum solution.
Then we return to calculating the potential energy ( ) e U X and repeat until ( ) e U X 0 or the complete iteration.If the system ( ) e U X is still not 0 when the iteration is complete, we reduce the number of solder joints N and iterate them again.Finally, we determine the maximum number of solder joints ( ) Max N .

Results
The described algorithm was implemented by C++ programming and tested on a computer with Radeon 3.0 GHz and 16 G RAM.The solder joints layout process is shown in Figure 6: (a) is the random initial solution generated, and it can be seen that many solder joints overlap; (b) is the result of 50 iterations, and the solder joints layout becomes uniform, but there are still some overlapping joints; (c) is the result after 300 iterations, the solder joints layout is completed, the electrical parameter constraints are satisfied, and the algorithm converges; (d) is the optimal solution retained during the iterations.Since the current approach taken for the current study of the solder joint layout problem is generally manual layout, which is inefficient in the face of relatively largescale problems, the results obtained are not always good.There is currently no relevant algorithm in the industry so this paper only shows the results obtained by our algorithm.Table 1 shows the results of the three examples tested by this algorithm.It can be seen that the number of solder joints has decreased as the iteration progresses, and the maximum number of solder joints can be finally determined after 300 iterations.It can also be seen that the space utilization of the obtained results is relatively high and can handle different shapes of frame plate shapes, and the final results of examples 2 and 3 are shown in Figure 7. Max (N) is the maximum number of solder joints that can be accommodated in the layout area obtained in the examples, and the space utilization is the space occupancy of the solder joints when the optimal layout (after processing the constraints) is applied.It can be seen that the algorithm in this paper gives better results and obtains higher space utilization.The method proposed in this paper has been able to solve the problem of the automatic layout of solder joints (with electrical parameter constraints) in complex polygons, while other papers can only solve the problem of equal circle packing in simple areas, such as squares, circles, and square triangles (without circuit constraints).

Conclusions
The article presents an automated layout algorithm for maximizing the number of solder joints on PCBs and LGA framework boards.The experimental results demonstrate that the proposed algorithm is both practical and feasible, achieving a spatial utilization rate of up to 95.5% for maximizing the number of solder joint layouts.
constraint 2) into a solder joint of radius R without overlap between them.

Figure 2 .Figure 3 . 2 B
Figure 2. The process of the distance between solder joints Handling of solder joints and area boundary constraints For the constraint between the solder joints and the region boundary, if 2 d l  , the boundary region shrinks inward 2 d l  ; if 2 d l  , the boundary region expands outward 2 l d  .Constraint 3) is transformed into the solder joint with radius R that does not exceed the boundary of the layout area.As shown in Figure 3, the boundary vertex ( ) P P M  and the line segment 1 2 , B B adjacent to it are known, and make the parallel lines with the line spacing 2 D l d   on the same side 1 2 , B B .The intersection point of the two lines is noted as Q, which is the vertex of the layout area after expansion inwards or outwards.

Figure 4 .
Figure 4. Circular dense packing Figure 5 shows the flowchart of the algorithm.