CIS-based system for acquiring and transmitting image data

The design utilizes a network of CIS lines (DL520-09UHM-S) to design an image data acquisition and transmission system. Using the STM32F1 chip as the control core, the hardware circuit of STM32F1 with DL520-09UHM-S, A/D converter chip, FIFO cache chip and CAN transceiver chip is designed, and the parameters of each device are controlled to complete the acquisition and transmission of image data. The PC processes the data through software to derive the acquired image data.


Introduction
The image sensors are classified according to the production process in CMOS [1] (Complementary Metal Oxide Semiconductor) and CCD [2](Charged Coupled Device).The CCD image sensor, with its low sound, high sensitivity, and low dark current, has long dominated the image sensor market.Compared to CCD image transducers, CMOS image transducers have the advantage of low energy consumption and low cost.CIS is a new type of linear array optoelectronic element of the CMOS type, which is widely used in bill counters, bill scanners, and document scanners, with the advantages of high integration, compactness, small size, no additional light source, and no geometrical distortion [3] [4].CIS is a linear sensor with its own light source, which can be scanned once to obtain one line of image information [5], and this feature can be used to capture the image information of the object of study and process it to obtain fast and accurate measurement results [6].The image data acquisition and transmission system designed in this paper uses a single-channel high-speed CIS sensor to acquire image data, and transmits the data to a computer for processing via a high-speed CAN bus.The system is a good implementation of acquiring and transmitting CIS images, with excellent real-time performance.

System Architecture.
The system comprises a data acquisition component, a microcontroller component, a CAN bus, and a computer.The entire process of acquiring and transmitting image data is performed using the ST STM32F1 serial MCU.Under the combined action of the CIS drive signal, A/D drive signal and FIFO write control signal from the STM32F1, the single channel analogue signal from the CIS is converted into a digital signal by A/D and then cached in the FIFO, and the STM32F1 stores the data in the internal RAM by controlling the FIFO read signal and finally transfers the data to the computer for processing via the CAN bus. Figure 1 shows the basic layout of the system.

System for acquiring and transmitting image data.
The image data acquisition and transmission system includes a CIS interface control module, an ADC conversion module, a FIFO data cache module, and a CAN bus data transmission module.

Design of the CIS interface command module
The system uses the LITEON-SEMI DL520-09UHM-S CIS Line Matrix with a scan width of 216 mm.The detector has an effective pixel count of 2592 per frame line in 300DPI mode and 5184 per frame line in 600DPI mode.The CIS timing diagram [7] is shown in Figure 2.

Design of the ADC conversion module
The analog signal from the CIS output must be converted into a digital signal by the ADC before being processed by the STM32F103.This system uses the HT82V36 chip from Holtek [8], a fully integrated analogue signal processor with four types of internal registers, namely Configuration, MUX, PGA, and Offset, which allow the STM32F103 to configure the HT82V36 to operate in different modes.When writing a configuration to a register, the SLOAD level is first pulled low, then 16 clock SCLKs are generated and the corresponding SDATA is written at the rising edge of each SCLK.The operating timing in single-channel SHA mode is shown in Figure 4. Analog input is the analog output signal of the CIS, CDSCLK2 is the CDS data clock pulse input, and ADCCLK is the sample clock input A/D.They are generated by the STM32F103 and the output data is the numerical output signal which is connected to the FIFO data buffer interface.The HT82V36 and STM32F103 connection circuit is shown in Figure 5.

Design of the FIFO cache module
FIFO (First Input First Output) can effectively solve the problem of shifting between STM32F103 playback speed and ADC output speed, and achieve the goal of inter-clock domain transmission.The system utilizes Averlogic's AL422B cache chip, which has a capacity of 384 KB.CIS acquires a line of image pixel data with a total of 3000 pixels, each pixel occupies 2 bytes, a total of 6000 bytes, using AL422B fully meets the requirements of caching multiple lines of data.The timing diagrams [9] of the AL422B are shown in Figure 6 and Figure 7.
When the WE signal is low, the write pointer reset signal is controlled to allow write operations, and data is entered into memory on the rising edge of each WCK write clock signal, followed by the write pointer automatically pointing to the next address to store the next data.The timing of read and write operations is similar.The FIFO and STM32F103 connection circuit is shown in Figure 8.

Design of the image data delivery module
The system is based on CAN bus transmission.CAN is an ISO international standardized serial communication protocol with two standards: ISO11898 standard and ISO11519-2 standard, of which ISO11898 is for high-speed communication standard with a communication rate of 125Kbps~1Mbps, while ISO11519-2 is for low-speed communication standard with communication rate below 125Kbps [10].The system uses the PHILIPS TJA1050 chip, ISO11898, and the physical layer characteristics of the CAN bus, as shown in Figure 9.The CAN controller determines the bus level based on the potential difference between the two buses (CAN High and CAN Low), which are divided into explicit level "0" and implicit level "1".A voltage difference of approximately 2.5 V between CAN High and CAN Low indicates a dominant level of "0", and a voltage difference of 0 V indicates a recessive level of "1".In the bus, the dominant level has priority, and as long as one-unit outputs a dominant level, the bus is dominant.Only if all units output a recessive level, the bus is recessive.The TJA1050 and STM32F103 connection circuit is shown in Figure 10.

Software design and computational treatment of data results
The STM32F103ZET6 chip, a 32-bit microprocessor based on the ST ARM Cortex-M3 core, is used as the main chip in the bottom computer [11].The software design of the bottom PC was performed in the MDK5 environment.The program module includes the hardware initialization module, the CIS data acquisition module, the ADC conversion module, the FIFO data cache module, and the CAN bus data transmission module.The software flow chart is shown in Figure 11.The software simulation waveform diagram is shown in Figure 12. (1) Module for hardware initialization.It includes system clock initialization and GPOI function initialization.The HLA library is called to configure the STM32-related registers.
(2) Module for acquiring CIS data.After initializing the start pulse SI period at 0.75 ms and the CLK operation clock at 4 MHz, the CIS will output an analog signal for each clock when it receives external light within 125~2716 clocks, and the analog signal will be sent to the ADC chip for analog-to-digital conversion.
(3) Module for ADC conversion.The HT82V36 write timing is initialized to write 16 bits of data, including one write control bit, three registry addresses, three inactive bits, and nine bits of config registry data.The HT82V36 write timing simulation waveform is shown in Figure 12(a).The first line of the waveform is SDATA, the second line is SCLK and the third line is SLOAD.Initializing CDSCLK2 and ADCCLK, the simulation waveform is shown in Figure 12(b).The first line of the waveform is the CIS running clock, the second line is CDSCLK2 and the third line is ADCCLK.The signal is sampled when the CDSCLK2 clock is high and retained for a certain time before sampling.During the hold time, ADCCLK outputs high 8 bits of data when it is high and low 8 bits of data when it is low.The output data is cached into the FIFO.
(4) Module for FIFO data cache.The write timing waveform simulation is shown in Figure 12(c).The first line of the waveform is WCK, the second line is WRST, and the third line is WE.The readtiming waveform simulation is shown in Figure 12(d).The first line of waveform is OE, the line second is RCK, and the third line is RRST.When SI=1, it means start scanning.The WRST and WE of the FIFO are controlled to allow the FIFO to write data.When the next SI=1, it indicates that a row of data scanning is complete, data writing is prohibited, and the FIFO read reset and read enable are controlled to allow the FIFO to read data.The FIFO is controlled to read clock, read the 8-bit data cyclically, and store it in the RAM of STM32F103.
(5) Module for CAN bus transfer data.Firstly, we enable the CAN clock.Then we call the HAL library to configure the relevant registers and set the CAN operating mode, baud rate and registers.Finally, we design the transmit function to cyclically send the data in RAM to the upper computer.
Figure 13 shows the experimental environment.The image data with different light intensities were collected and the results obtained after processing using MATLAB are shown in Figure 14.

Conclusion
In this article, the STM32F103 microcontroller with CIS core and ARM Cortex M3 is used as the central feature of the system.Using the HT82V32 for analogue to digital signal conversion, the FIFO is used for data caching and the CAN bus for data transmission, and a high accuracy and high-speed image data acquisition and transmission system is designed.Experiments show that the CIS image data acquisition and transmission system designed in this paper solves the problem of high-speed image acquisition and transmission.The system uses only one MCU to implement training and control for each module.The system is highly integrated, which in turn reduces the complexity of the system, and can be applied to systems that require real-time image information acquisition to measure data in the field of high-speed vision inspection.

Figure 1 .
Figure 1.Block diagram of the system.

Figure 2 .Figure 3 .
Figure 2. The timing diagram of CIS.CLK is the CIS 4 MHz operation clock; SI is the CIS line sweep signal, which controls the CIS acquisition line period.Each high pulse of SI marks the start of a new line of image acquisition by the CIS; SIG is the output analogue signal, when the SI signal is pulled down by 124 clock cycles, SIG starts to produce a valid output, and the signal output within 125 to 2716 clock cycles is a valid signal.The connection circuit between the CIS and the STM32F103 is shown in Figure 3.The STM32F013 controls the on/off of triode Q1, triode Q2 and triode Q3 via three pins.When these triodes are high, the triode is on and the LEDs in the CIS emit light.Different LEDs emit light of different intensities and each DOT in the CIS will get the corresponding red, green, and blue light signals.The three light signals are processed internally by the CIS to obtain an analogue voltage signal, which is transmitted to the HT82V36 via the SIG pin.