Design and Performance Optimization of InGaAs/InAlAs Dopingless Tunnel Field-effect Transistor

In this work, an InGaAs/InAlAs dopingless tunnel field-effect transistor is designed and systematically examined through numerical simulations. In line with the charge plasma concept, the proposed device can not only create a p-n-i-n structure without doping to enhance electron tunneling but also effectively overcome issues caused by doping such as random doping fluctuation, high thermal budget, etc. By investigating the effects of the HfO2 length (L H), the source-side channel length (L sc), and the source-drain electrodes structure on the proposed device, it concludes that the best device characteristic can be acquired when L H is located between 110 nm and 128 nm, L sc=4 nm, and double source-drain electrodes are adopted.


Introduction
As semiconductor device integration is improved and device dimension is reduced, MOSFETs are gradually close to the physical limit.Tunneling field effect transistor (TFET) looked upon as a likely device to continue Moore's law, has received a lot of attention by reason of its low-power consumption characteristic and CMOS compatibility [1][2][3].However, the low on-state current (I on ) constrains traditional Si-based TFETs' development.To solve this issue, a novel p-n-i-n TFET has been proposed [4][5][6], which is usually realized by creating a narrow N + -pocket in the source-side channel region for the traditional TFETs.However, the realization of the N + -pocket in manufacturing needs the process of dual-material gate or ion implantation, which will significantly increase the difficulty of device manufacturing so as to reduce the product yield rate.In addition, traditional Si-based TFETs and p-n-in TFETs usually belong to doped TFETs, which will suffer from some problems degrading device performance such as random doping fluctuation, high thermal budget, and difficulty in forming abrupt tunneling junction in source/channel interface.
To solve the issues aforementioned, an InGaAs/InAlAs dopingless TFET (HDL-TFET) is proposed in this paper.The drain, source, as well as the N + -pocket of HDL-TFET, are created according to the charge plasma concept without doping [7], which can avoid many problems caused by doping, improve device performance, and simplify fabrication.The use of InGaAs/InAlAs heterojunction with lattice matching and HfO 2 /SiO 2 hetero-dielectric can not only improve the I on but also suppress the ambipolar current (I amb ) and off-state leakage current (I off ).In this paper, the effects of the source-side channel length (L SC ), HfO 2 length (L H ), and electrode structure on HDL-TFET are investigated.

Devices Structure and Simulation Methods
The cross-sectional view and corresponding structure parameters for the proposed HDL-TFET are displayed in Figure 1, where the drain, source, as well as N + -pocket regions, can be generated in line with the charge plasma concept.The concept concludes two important parts [7]: 1) when the work function of electrodes is less than or greater than that of the semiconductor material respectively, electrons or holes layer can be induced in the corresponding semiconductor material, respectively; 2) the thickness of semiconductor material needs to be smaller than the Debye length.Therefore, to create the N + -type drain and P + -type source regions respectively, hafnium with a work function of 3.9 eV and platinum with a work function of 5.93 eV can be picked as the drain and source metal electrodes respectively [8].The thickness of semiconductor material is designed to be 10 nm to maintain uniform carrier distribution.The semiconductor material of the source region and source-side channel (SC) is In 0.53 Ga 0.47 As, but the one in the drain region and drain-side channel (DSC) is In 0.52 Al 0.48 As.Since these two materials are of different forbidden bandwidths and affinities, choosing the gate electrode with the appropriate work function can create the N + -pocket in SC, and its width is approximately equal to L SC .All simulations are performed by Silvaco-Atlas numerical simulator.Models included in [9] are referred to in the simulations, such as the strain model, the Lombardi mobility and field-dependent mobility models, the non-local tunneling model, etc.

Influence of length of source-side channel on HDL-TFET
Figure 2(a) shows the I off and I on values under different L sc s, which can be obtained from the transfer characteristic curves.As L sc increases, I off takes on a monotonically increasing trend, and I on increases sharply first and then decreases slightly.To explain both change trends, the energy bands (not shown) are calculated.For a better explanation, two kinds of tunneling are defined: 1) electrons in the valence band of the P + -type source region tunneling into the conduction band of SC is defined as SSTtunneling, and 2) electrons in the valence band of the P + -type source region tunneling into the conduction band of DSC is defined as SDT-tunneling.According to Equation ( 1) in [10], SST tunneling is far stronger than SDT tunneling in the off-and on-states.In the off-state, only SDTtunneling exists when L sc = 0 nm, but when L sc > 0 nm, SST-tunneling is also turned on and becomes stronger with the increase of L sc , both of which result in the change trend of I off .In the on-state, SSTtunneling enhances with L sc and saturates when L sc > 10 nm, but SDT-tunneling weakens with the increase of L sc .As a result, the mutual restriction of these two tunnelings causes the above trend in I on .When the drain current (I ds ) reaches 0.1 μA/μm, its corresponding gate voltage (V gs ) is called the subthreshold voltage (V th ).It is found from Figure 2(b) that V th decreases as L sc increases, which is because the increasing L sc enlarges the tunneling region so as to enable the device to be turned on at a lower V gs .Figure 2(c) shows that with the increase of L sc , I on /I off decreases monotonically, while the average subthreshold swing (SS avg ) decreases first and then increases.By compromising these device parameters, HDL-TFET can obtain the best characteristic when L sc =4 nm, where I off = 8.5×10 −14 A/μm, I on = 1.67×10 −5 A/μm, V th = 0.22 V, and SS avg = 36.6mV/decade.where I off and I on can be obtained and drawn in Figure 3(b).Investigation illustrates that I on reaches the minimum value when L H =103 nm, which is because the dielectric SiO 2 beneath the gate causes a relatively low electric field (E) in the tunneling junction.I on increases with L H , which is due to that the dielectric beneath the gate is gradually replaced by HfO 2 so as to enhance the E in the tunneling junction.Moreover, as L H increases, I off increases rapidly first, then slows down, and saturates when L H >128 nm. Figure 3(c) shows the I amb values under different L H s, which are also extracted from Figure 3(a).I amb basically keeps stable when L H ≤128 nm, but it increases significantly when L H further increases.It is because HfO 2 gradually extending to the drain enhances the E in the tunneling junction between the N + -type drain region and the channel region, eventually enhancing the tunneling probability of holes in the conduction band of the N + -type drain region.Particularly, when L H =168 nm, the dielectric between the gate and drain is completely replaced by HfO 2 , which makes C gd and C gg increase significantly.Moreover, the dependence of transconductance (g m ) on L H is investigated (not shown).Results demonstrate that the peak of g m increases obviously with L H .With the increase of L H , V gs corresponding to the peak of g m decreases first and then saturates, which indicates that the increasing L H is beneficial for HDL-TFET to operate in the low powerconsumption state.Figures 4(b) and 4(c) exhibit the gain bandwidth product (GBP) and cut-off frequency (f T ) of HDL-TFET with different L H s, respectively.It is observed that with the increase of L H , both GBP and f T increase first, and begin to saturate when L H >110 nm.However, when L H =168 nm, GBP and f T show significant degradation due to the increase of parasitic gate capacitance far exceeding V ds = 0.3 V that of g m .Therefore, when L H is located between 110 nm and 128 nm, HDL-TFET can obtain better DC and RF performance and effectively suppress I amb , especially when L H =128 nm, the optimal f T and GBP approach 13 GHz and 5.23 GHz, respectively.show electron and hole concentration profiles for the two TFETs near the top gate and bottom gate, respectively.For HDL-TFET, the carrier concentration near the top gate is not equal to that near the bottom gate.It is because holes and electrons that existed in the source and drain regions respectively, can only be induced through the top source and drain electrodes, respectively.Moreover, the bulk material near the bottom gate is relatively far from the top electrodes, which reduces the carrier concentration induced in this region, eventually degrading the tunneling that occurred near the bottom gate.However, for DEHDL-TFET, the carrier concentration near the top gate is basically the same as that near the bottom gate, which indicates that the same tunneling condition is possessed at the top and bottom of the bulk material, thereby eliminating unbalanced carrier distribution caused by the single source-drain electrodes, and eventually enhancing the tunneling of carriers near the bottom gate.Moreover, we can also interpret the increase of I on in view of the perspective of the energy band.distance near the bottom gate, thus a higher tunneling current can be obtained in this region, significantly boosting I on .and 7(c), both f T and GBP of DEHDL-TFET have a significant increase compared with HDL-TFET, which can be interpreted by C gg and g m .f T and GBP are proportional to g m , but inversely proportional to C gg .Since for DEHDL-TFET, the increase of g m is much greater than that of C gg , its peak f T and GBP (18.4 GHz and 9.7 GHz) are increased by 41.4% and 85.5% respectively than that of HDL-TFET (13 GHz and 5.23 GHz).It follows that the dual source-drain electrodes can significantly boost the device performance of HDL-TFET.

Conclusions
In summary, an InGaAs/InAlAs dopingless TFET (HDL-TFET) is investigated in detail by numerical simulations.Researches show that when L sc =4 nm, optimal device performance can be obtained, where I off =8.5×10 −14 A/μm, I on =1.67×10 −5 A/μm, V th =0.22 V, and SS avg =36.6 mV/decade.Moreover, the effect of L H on the proposed HDL-TFET is investigated, and results demonstrate that only when L H is located between 110 nm and 128 nm, it can maintain good DC and RF performance and effectively suppress I amb .In particular, when L H =128 nm, the optimal f T and GBP approach 13 GHz and 5.23 GHz, respectively.Further, the influence of the source-drain electrode structure on HDL-TFET is examined, and investigations indicate that electron tunneling near the bottom gate can be enhanced by the double source-drain electrodes, thereby significantly improving device performance.Compared with HDL-

Figure 1
Figure 1 Schematic illustration of the proposed device

Figure 2
Figure 2 Dependence of (a) I off and I on , (b) V th , and (c) I on / I off and SS avg with respect to L sc 3.2 Effect of HfO 2 length on HDL-TFET Figure 3(a) illustrates HDL-TFET's transfer characteristic curves under different HfO 2 lengths (L H s),where I off and I on can be obtained and drawn in Figure3(b).Investigation illustrates that I on reaches the minimum value when L H =103 nm, which is because the dielectric SiO 2 beneath the gate causes a relatively low electric field (E) in the tunneling junction.I on increases with L H , which is due to that the dielectric beneath the gate is gradually replaced by HfO 2 so as to enhance the E in the tunneling junction.Moreover, as L H increases, I off increases rapidly first, then slows down, and saturates when L H >128 nm.Figure3(c) shows the I amb values under different L H s, which are also extracted from Figure3(a).I amb basically keeps stable when L H ≤128 nm, but it increases significantly when L H further increases.It is because HfO 2 gradually extending to the drain enhances the E in the tunneling junction between the N + -type drain region and the channel region, eventually enhancing the tunneling probability of holes in the conduction band of the N + -type drain region.

Figure 3 (Figure 4
Figure 3 (a) Transfer characteristic curves, (b) I on and I off , and (c) I amb , for HDL-TFET with different L H s Figure 4(a)shows the total gate capacitance (C gg ), the gate-drain capacitance (C gd ), as well as the gate-source capacitance (C gs ) under different L H s. Since the increase of L H improves the tunneling ability of electrons, the concentration of electrons in the channel increases, thereby increasing C gd .Particularly, when L H =168 nm, the dielectric between the gate and drain is completely replaced by HfO 2 , which makes C gd and C gg increase significantly.Moreover, the dependence of transconductance (g m ) on L H is investigated (not shown).Results demonstrate that the peak of g m increases obviously with L H .With the increase of L H , V gs corresponding to the peak of g m decreases first and then saturates, which indicates that the increasing L H is beneficial for HDL-TFET to operate in the low powerconsumption state.Figures4(b) and 4(c) exhibit the gain bandwidth product (GBP) and cut-off frequency (f T ) of HDL-TFET with different L H s, respectively.It is observed that with the increase of L H , both GBP and f T increase first, and begin to saturate when L H >110 nm.However, when L H =168 nm, GBP and f T show significant degradation due to the increase of parasitic gate capacitance far exceeding

Figure 4 (
Figure 4 (a) Parasitic gate capacitance, (b) GBP, and (c) f T , for HDL-TFET with L H = 103 ~168 nm 3.3 Effect of source-drain electrodes structure on HDL-TFET For comparison, the HDL-TFET with double source-drain electrodes (named DEHDL-TFET) is introduced and shown in Figure 5(a), and it has the same structural parameters as HDL-TFET.Transfer characteristic curves of HDL-and DEHDL-TFETs are plotted in Figure 5(b).I off of these two TFETs basically remains unchanged, while the I on of DEHDL-TFET approaches 2.37×10 −5 A/μm, about two times greater than that of HDL-TFET (1.24×10 −5 A/μm).Due to the introduction of sourcedrain electrodes at the bottom, the probability of electrons in the valence band of the P + -type source region near the bottom-gate tunneling into the conduction band of the channel can be enhanced, resulting in an increase in I on .

Figure 5 (
Figure 5 (a) Schematic illustration of DEHDL-TFET, and (b) transfer characteristic curves of two devices Figures 6(a) and 6(b)show electron and hole concentration profiles for the two TFETs near the top gate and bottom gate, respectively.For HDL-TFET, the carrier concentration near the top gate is not equal to that near the bottom gate.It is because holes and electrons that existed in the source and drain regions respectively, can only be induced through the top source and drain electrodes, respectively.Moreover, the bulk material near the bottom gate is relatively far from the top electrodes, which reduces the carrier concentration induced in this region, eventually degrading the tunneling that occurred near the bottom gate.However, for DEHDL-TFET, the carrier concentration near the top gate is basically the same as that near the bottom gate, which indicates that the same tunneling condition is possessed at the top and bottom of the bulk material, thereby eliminating unbalanced carrier distribution caused by the single source-drain electrodes, and eventually enhancing the tunneling of carriers near the bottom gate.Moreover, we can also interpret the increase of I on in view of the perspective of the energy band.Figure6(c) shows that DEHDL-TFET has a smaller tunneling Figures6(a) and 6(b) show electron and hole concentration profiles for the two TFETs near the top gate and bottom gate, respectively.For HDL-TFET, the carrier concentration near the top gate is not equal to that near the bottom gate.It is because holes and electrons that existed in the source and drain regions respectively, can only be induced through the top source and drain electrodes, respectively.Moreover, the bulk material near the bottom gate is relatively far from the top electrodes, which reduces the carrier concentration induced in this region, eventually degrading the tunneling that occurred near the bottom gate.However, for DEHDL-TFET, the carrier concentration near the top gate is basically the same as that near the bottom gate, which indicates that the same tunneling condition is possessed at the top and bottom of the bulk material, thereby eliminating unbalanced carrier distribution caused by the single source-drain electrodes, and eventually enhancing the tunneling of carriers near the bottom gate.Moreover, we can also interpret the increase of I on in view of the perspective of the energy band.Figure6(c) shows that DEHDL-TFET has a smaller tunneling

Figure 6
Figure 6 Electron and hole concentration profiles near (a) the top gate and (b) the bottom gate, and (c) energy band profiles near the bottom gate, for HDL-TFET and DEHDL-TFET Figure 7(a) illustrates the C gg of HDL-TFET and DEHDL-TFET at different V gs s.It is found from the figure that DEHDL-TFET possesses a larger C gg , which is because the introduction of source-drain electrodes at the bottom increases the C gs and C gd .Similarly, the increase in g m of DEHDL-TFET is also attributed to this reason.As shown in Figures 7(b) and 7(c), both f T and GBP of DEHDL-TFET have a significant increase compared with HDL-TFET, which can be interpreted by C gg and g m .f T and GBP are proportional to g m , but inversely proportional to C gg .Since for DEHDL-TFET, the increase of g m is much greater than that of C gg , its peak f T and GBP (18.4 GHz and 9.7 GHz) are increased by 41.4% and 85.5% respectively than that of HDL-TFET (13 GHz and 5.23 GHz).It follows that the dual source-drain electrodes can significantly boost the device performance of HDL-TFET.
Figure7(a) illustrates the C gg of HDL-TFET and DEHDL-TFET at different V gs s.It is found from the figure that DEHDL-TFET possesses a larger C gg , which is because the introduction of source-drain electrodes at the bottom increases the C gs and C gd .Similarly, the increase in g m of DEHDL-TFET is also attributed to this reason.As shown in Figures7(b) and 7(c), both f T and GBP of DEHDL-TFET have a significant increase compared with HDL-TFET, which can be interpreted by C gg and g m .f T and GBP are proportional to g m , but inversely proportional to C gg .Since for DEHDL-TFET, the increase of g m is much greater than that of C gg , its peak f T and GBP (18.4 GHz and 9.7 GHz) are increased by 41.4% and 85.5% respectively than that of HDL-TFET (13 GHz and 5.23 GHz).It follows that the dual source-drain electrodes can significantly boost the device performance of HDL-TFET.

Figure 7 (
Figure 7 (a) C gg , (b) f T , and (c) GBP of HDL-TFET and DEHDL-TFET -TFET possesses about two times increase in I on , 41.4% and 85.5% improvement in f T and GBP, respectively.