A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS

A calibration-free 12-bit 120-MS/s 2-stage pipelined successive approximation register (pipelined SAR) analog-to-digital converter (ADC) is presented in this paper. In asynchronous SAR ADCs, capacitive digital-to-analog converters (CDACs) are designed with bottom-plate sampling to improve sampling accuracy and split-capacitor array to save switching energy. Furthermore, both reference scaling technique and a PVT-stabilized closed-loop residue amplifier are implemented in this design to obtain an accurate inter-stage gain, enabling no additional calibration required in the pipelined SAR ADC. The prototype ADC in 40nm CMOS technology achieves a peak signal-to-noise-distortion ratio (SNDR) of 73.4 dB and 88.91dB spurious-free-dynamic-range (SFDR) at 120 MS/s sampling rate, consuming 4.88 mW power from 0.9 V supply voltage, and corresponding to an excellent figure-of-merit (FoM) of 10.7 fJ/conv.-step.


Introduction
An analog to digital converter (ADC) is an electronic circuit which converts continuous signals to discrete digital signals.It is a bridge from real world to digital world and widely used in various applications like wireless communication, image processing, internet of things (IoT), information storage and machine learning.With the increasing demand for next-generation communication, the trend of developing low-power, high-speed, high-resolution ADCs has emerged, where pipelined SAR ADCs have become popular for their excellent energy-efficiency.Pipelined SAR ADC multiplies the speed of single SAR ADC and keeps the low and dynamic power nature of the SAR architecture [1].Although the pipelined SAR architecture is regarded as a good choice, there is several challenges left to be overcome including the long bit-cycling time, reference voltage recovery and capacitor mismatch, etc.
Several techniques have been put forward to solve these problems.Asynchronous SAR ADCs use clock-generating logic circuit to eliminate the stand-by time of ADC and improve operation speed compared with synchronous circuit.Loop-unrolled structure employs a higher speed-control logic by using multiple comparators and unfolding a single comparator clock loop [2].Redundant technique is proposed to relieve settling limitation and compensate decision error during bit-cycling [3].Capacitor splitting can achieve symmetric switching and constant common-mode voltage to alleviate reference voltage recovery and increase the conversion speed [4].
High-performance Pipelined SAR ADCs place high demands on residue amplifiers.Both dynamic amplifier and ring amplifier consume less power consumption but are sensitive to PVT variations.To avoid the use of calibration circuit that increases overall circuit complexity, this work employs a PVTstabilized static closed-loop residue amplifier to obtain accurate inter-stage gain.

Pipelined SAR ADC architecture
The pipelined SAR ADC architecture is shown in Fig. 1.It consists of a 5-bit first stage SAR ADC, an 8-bit second stage SAR ADC, a residue amplifier and a digital logic block.1-bit redundancy is introduced to tolerate some circuit errors of the first stage, relaxing noise, setting time and offset requirements of the first SAR quantizer.By halving the reference voltage of the second stage ADC and setting 1-bit redundancy, the inter-stage gain is reduced to 8 but not 16, which greatly relieves the design complexity of the residue amplifier and reduces its power consumption.In this design, a static closed-loop residue amplifier with gain of 8 is used to connect the first and second stages.The digital logic block combines the digital outputs of two SAR ADCs and produce final digital codes of the whole ADC.The inter-stage amplifier amplifies the residue voltage with a gain of 8.The signal range of 2nd-stage SAR ADC is 0.9V, it resolves the amplified residue voltage with 8-bit resolution (D2).The LSB size of the second SAR ADC is about 3.516 mV.So the digital code can be calculated by D_1×32+D_2 with 1-bit redundancy.
The schematic of the first SAR ADC shown in Fig. 3 consists of a capacitive DAC, bootstrapped switches, a dynamic comparator and SAR-control logic circuit.To alleviate nonidealities of sampling switches, the SAR ADC uses bottom-plate sampling which switches continuously between negative and positive reference voltages.The capacitive DAC uses capacitor splitting array which can guarantee a stable common-mode voltage.The structure of the second stage SAR ADC is the same as that of the first stage ADC.

Capacitive DAC
Both SAR ADCs use the same CDAC structure, the 5-bit CDAC of the first stage is introduced as an example.In Fig. 3, the CDAC of the SAR ADC is implemented by bottom-plate sampling and splitcapacitor array.Bottom-plate sampling transforms charge-injection effect into a fixed offset at the output, which can be easily eliminated by a fully differential structure.Split-capacitor switching increases the conversion speed and eliminates the need for a common-mode voltage for the CDAC during the reset phase.4-6 show the schematic of the proposed split-capacitor switching timing in sampling, charge transfer, and reference settling phases, respectively.All-bit capacitors except for LSB and dummy ones are split into two equal sub-capacitors to perform the splitting monotonic switching method.In the sampling phase (Fig. 4), the bottom plates of all capacitors capture the input signal via the bootstrapped switches.At the same time, the top plates of all capacitors are connected to VCM.In the conversion phase, one sub-capacitor is connected to VRP and the other to VRN in each bit capacitors.The LSB capacitor is connected to VRP and the dummy capacitor to VRN (Fig. 5).After the DAC is settled and its output is compared by the comparator, the bottom plate of the MSB capacitors reswitched to VRP or VRN, according to the comparison result (Fig. 6).The settling-comparisonswitching operation iterates until the successive approximation process completed.The split-capacitor structure is more power-efficient as there is no continuous switching between positive and negative reference voltages.Also the on-resistances of the bottom-plate switches become smaller which can reduce the DAC settling time.In the sampling phase, the top plates of CDAC are connected to VCM, and disconnected after sampling.As the top plates of capacitors are directly connected to the comparator inputs and floating during the conversion phase, charge injection and clock feed-through are introduced during the turning off of VCM switches.In this design, optimized VCM switches are applied to suppress these nonidealities, as shown in Fig. 7. BK is a bootstrapped switching signal that keeping the on-resistances of the four switches linear and small.When the switches turned off, the charge injected into the capacitor top plates is a fixed offset, which is further cancelled by symmetrical placement of transistors M1, M2, M3, and M4.The transistors M5 and M6 are two MOST capacitors controlled by signal NK, which is an inversion of BK.M5 and M6 have two roles, first to appropriately increase the input common-mode voltage of the comparator through capacitive coupling, and to cancel out the voltage variation caused by clock feedthrough.By sizing transistors M1~M6 carefully, the influences of charge injection and clock feed-through can be minimized to the required level.

Asynchronous clock generation circuit
Asynchronous SAR ADCs use clock-generating logic circuit to remove stand-by time of ADC and boost operation speed.Fig. 8 shows the schematic of asynchronous clock generation block.The generation circuit forms a structure similar to ring oscillator by using a dynamic comparator, a threeinput AND-gate, and a delay module.The comparator in this design is controlled by an asynchronous clock, and the sampling clock is provided outside the ADC.As shown in Fig. 8, the signal GT is used to control the number of clock cycles generated.When GT is low, CKC is low, Q and QB are high.When GT becomes high, since Q and QB are high, the output of three-input AND-gate is high.The CKC changes from low to high and triggers the comparator.When the comparator outputs the result, the levels of Q and QB are opposite, so the output of the three-input AND-gate is low, causing CKC to become low.When the comparator is reset, Q and QB become high.Asynchronous clock is generated by alternating switching.

Residue amplifier
Considering the required gain and loop stability, traditional switched-capacitor amplifier is chosen as residue amplifier in our design, as shown in Fig. 9.The working process can be divided into reset phase and amplification phase.In the reset phase, switch Φ1 is off and Φ2 is on, input and output of the amplifier are shorted with a feedback factor of 1, the feedback capacitor Cf is pre-charged to VCM.In the amplification phase, switch Φ1 is on and Φ2 is off.Due to the negative feedback, the charge on the input capacitor Cin will be transferred to the feedback capacitor Cf.According to the conservation of charge, the output differential-mode voltage is amplified by Cin/Cf compared with input differential-mode voltage.Therefore, by adjusting the ratio between Cin and Cf, the residue voltage can be amplified correctly.
The error due to the finite gain of amplifier is 1/βA0.The finite gain error of the first stage of MDAC is usually less than half of the minimum resolution of the second stage of SAR ADC, so the open-loop gain of operational amplifier needs to reach the requirement: (2 Where β is the feedback coefficient, in this design β is set to 1/8.Assuming the amplification time of the inter-stage amplifier is t, so the output voltage is written as: Same as the finite gain error, the establishment error is usually less than half of the second stage of SAR ADC: As a result, the unit gain bandwidth needs to attain the requirement: In this work, 5.1333ns is assigned to amplify the residue voltage.From (5), the unit gain bandwidth of amplifier should be more than 1.589GHz.Considering the non-ideal effect of CDAC in the first stage SAR ADC, the actual inter-stage gain may be slightly greater than 8 to compensate for the smaller residue voltage.By adjusting the feedback capacitor Cf, the open-loop gain of amplifier is reduced to about 67dB from (2) .
To achieve high gain and high bandwidth simultaneously, a gain-boosted folding cascode amplifier is utilized in this work, as shown in Fig. 10-11.It is composed of a main folding cascode amplifier and two auxiliary amplifiers GA and GB, which are modified telescope structures.The AC simulation results of the amplifier is shown in Fig. 12.The designed gain-boosted amplifier achieves 67.2 dB gain, 2.95 GHz GBW, and 67.7°phase margin.

Simulation results
The proposed pipelined SAR ADC has been designed and simulated in 40nm CMOS technology with a 0.9 V supply voltage.The input signal is a 1.8V peak-to-peak sinusoidal waveform with varying frequency, and the sampling rate is 120 MHz.

Figure 1 .
Figure 1.Architecture of the 12b Pipelined SAR ADC Fig. 2 shows the timing diagram of the presented pipelined SAR ADC with a sampling rate of 120 MS/s.Firstly, the analog input voltage is sampled in 2ns by the first ADC.The next step is evaluation phase for 5-bit digital codes allocated with 1.2ns.It takes 3.2ns to process the first 5-bit digital code and generate residue voltage in one period.In the rest 5.1333ns, the inter-stage amplifier amplifies the residue voltage and the second stage ADC samples the amplified residue voltage at the same time.In the operation of the second ADC, 3.2ns is assigned to resolve the 8-bit digital code.

Figure 2 .
Figure 2. Timing diagram of the pipelined SAR ADC This design targets to achieve 12-bit resolution with a differential input signal range of 1.8V at 120 MS/s.To achieve 12-bit accuracy, a capacitive DAC array with 1pF single-ended total capacitance is

Figure 3 .
Figure 3. Schematic of the 1 st stage 5bit SAR ADC Fig.4-6show the schematic of the proposed split-capacitor switching timing in sampling, charge transfer, and reference settling phases, respectively.All-bit capacitors except for LSB and dummy ones are split into two equal sub-capacitors to perform the splitting monotonic switching method.In the sampling phase (Fig.4), the bottom plates of all capacitors capture the input signal via the bootstrapped switches.At the same time, the top plates of all capacitors are connected to VCM.In the conversion phase, one sub-capacitor is connected to VRP and the other to VRN in each bit capacitors.The LSB capacitor is connected to VRP and the dummy capacitor to VRN (Fig.5).After the DAC is settled and its output is compared by the comparator, the bottom plate of the MSB capacitors reswitched to VRP or VRN, according to the comparison result (Fig.6).The settling-comparisonswitching operation iterates until the successive approximation process completed.The split-capacitor structure is more power-efficient as there is no continuous switching between positive and negative reference voltages.Also the on-resistances of the bottom-plate switches become smaller which can reduce the DAC settling time.

Figure 7 .
Figure 7. Switch setting of top plates connected to VCM

Figure 8 .
Figure 8. Circuit of the asynchronous clock generation block

Figure 9 .
Figure 9. Architecture of the residue amplifier The performance of the amplifier directly affects the conversion result of the entire ADC.The accuracy and speed of ADC determine the open-loop gain and gain bandwidth of amplifier respectively.Assuming the open-loop gain of amplifier is A0, so the inter-stage gain can be expressed as: =

Figure 10 .
Figure 10.Detailed schematic of the main amplifier Fig. 13 and 14 give the simulated ADC spectrum with low-frequency and high-frequency inputs respectively.With a Nyquist input, the pipelined SAR ADC achieves an ENOB of 11.89 bits and an SFDR of 88.91dB without calibration.The presented ADC consumes 4.88 mW, leading to a Walden FOM of 10.7 fJ/conv.-stepand a Schreier FoM of 174.3 dB near the Nyquist frequency.The ADC performance is summarized and compared with state-of-the-art designs in TABLE I.

Figure 13 .
Figure 13.Simulated ADC Spectrum with 120MS/s sampling rate and 5.0MHz input

Table 1 .
Performance comparison This paper presents a low-power calibration-free pipelined SAR ADC in 40nm CMOS technology.Both reference scaling and PVT-stabilized residue amplifier techniques are implemented to generate accurate inter-stage gain without calibration.To optimize accuracy and power, the asynchronous SAR ADCs are implemented by bottom plate sampling and split-capacitor array.At a sampling rate of 120 MS/s, the pipelined SAR ADC achieves a SNDR of 73.36 dB and a SFDR of 88.91 dB with Nyquist input.The ADC consumes a total power of 4.88mW, leading to a Walden FoM of 10.7fJ/conv.-stepand a Schreier FOM of 174.3dB.