A Closed-Loop VCO-based 1-1 SMASH CT ΔΣ ADC Architecture

A novel closed-loop voltage-controlled oscillator (VCO)-based 1-1 sturdy multistage noise-shaping (SMASH) continuous-time ΔΣ ADC is presented in this paper. The proposed architecture uses VCOs as integrators and puts them in a closed loop to suppress the VCO nonlinearity. The multi-bit quantization is employed in the proposed architecture so that the requirement of a high over-sampling ratio (OSR) is relaxed while maintaining a high resolution. The architecture has been verified in MATLAB Simulink.


Introduction
Analog-to-digital converters (ADCs) are the bridge between the analog and digital worlds and they play a crucial role in many electronic systems such as the Internet-of-Things (IoT), wireless communications, and wearable devices.Oversampling (ΔΣ) ADCs have accelerated the rapid development of mobile applications over the past few decades with their high-resolution, relaxed-anti-aliasing advantages.And they are expected to drive a greater scale of electronic systems.However, new challenges also follow.To meet the tight power and area requirements in many emerging IoT applications, mixed-signal interfaces are increasingly integrated into systems-on-chip (SoCs) using more advanced processes.While advanced process brings some advantages to ADC designs as the power and area consumption of the digital circuits in the ADC is reduced and the speed is increased, it brings little benefit or even hurts to conventional analog circuits such as transconductance amplifiers (OTAs) in several ways.First, the transistor intrinsic gain decreases with channel length becomes shorter.Second, the power supply voltage scales down which leads to the signal swing reduction.Therefore, the Signal-to-Noise Ratio (SNR) will decrease.Third, with a smaller transistor size, poor device matching also leads to a drop in performance.In this case, the drawbacks of CMOS scaling is highly required to be compensated by several techniques such as multi-stage amplifiers, and complicated digital calibration techniques which is power and area consuming.
This fact calls for a new architecture that benefits from the CMOS scaling instead of being suffered from it.One of these architecture is time-domain (TD) ADC.Instead of processing the signal in the voltage domain, TD ADCs process and represent the signal using time-domain variables such as frequency, phase, and pulse width.Therefore, this architecture is more tolerant of low voltages.Additionally, since timing information can be processed through most digital structures, TD ADCs benefit from transistor scaling.Ring voltage-controlled oscillators (VCO)-based integrators and quantizers, which translate the input voltage or current signal to time and phase signal, are good candidates to realize in TD ADCs.VCO-based integrators provide infinite dc gain with ideal voltage-frequency integration.This voltagefrequency operation mitigate the finite gain error of traditional OTA-based integrators.Also, since the VCO-based quantizer inherently do multi-level quantization, compared with conventional Flash-based quantizer, both the comparator design and reference generation requirement are relaxed.Additionally, the VCO-based integrator and quantizer only consists of several digital logic gates, which are power efficient and scaling-friendly compared with conational analogue circuit.In this case, the performance of VCO-based ∆Σ ADCs improves naturally with CMOS scaling.Nevertheless, the highly nonlinear tuning response of the VCO raises practical concerns and challenges for designing VCO-based ADCs.Both foreground digital calibration based on look-up-table [1] and background digital calibration [2] based on replica matching all suffer from process variations.Additionally, the input signal swing is still limited by the nonlinearity of the VCO.In order to ensure the whole ADC performance is not limited by the nonlinearity of the VCO, the input swing of the ADC will be veritably reduced, leading to an overall SNR loss.Another way to solve the VCO nonlinearity issue is putting VCO into a closed loop.In this case, the signal swing of the VCO input is largely reduced by the feedback signal.Most existing close-loop VCO-based ∆Σ ADCs demonstrate state-of-the-art performance, but they are limited to only 1st-order noise shaping [3].Therefore, it presents a need to implement high-order VCO-based ∆Σ ADC.In order to extend the noise-shaping order, Ref. [4] combines the VCO-based quantizer with classic OTA-based integrators, but it sacrifices the powerefficiency and scaling-friendliness. Ref. [5] puts a VCO integrator in front of the VCO-based quantizer to boost the noise-shaping order.However, this cascade of integrators with feedback (CIFB)-based architecture is sensitive to PVT variation.A second-order purely VCO-based ∆Σ ADC leveraging the loop mechanism of a Digital Phase-Locked Loop (DPLL) is proposed by cascading two VCOs in one ∆Σ loop [6][7].By using only one ∆Σ loop, this architecture is more robust than Ref. [5].Nevertheless, the first VCO-based integrator consumes much power as the single-PFD structure is adopted in [7].Ref. [6] uses multi-PFD to reduce the power of the first VCO integrator but due to the multi-level output of the multi-PFD, the nonlinearity of the second VCO-based integrator raises practical concerns and challenges.A high-order purely VCO-based ∆Σ ADC using Multi-stage noise shaping (MASH) is reported in [8], but it suffers from analog and digital filter mismatch.To address this issue, Ref. [9] proposed a VCO-based ∆Σ ADC using Sturdy MASH (SMASH) [10], which eliminates the filter matching issue.However, Ref. [9] suffers from VCO nonlinearity issue as the VCO sees full signal swing.Also, the resolution of [9] is still limited by its single-bit quantization.In this paper, we propose a closed-loop VCO-based 1-1 SMASH ∆Σ ADC.The proposed architecture is highly linear and achieves high resolution with a low OSR.Compared to [9], the input swing at the first stage VCO integrator is much smaller as it is placed in the closed loop.Thus, the proposed architecture effectively solves the VCO nonlinearity issue.Also, adopting multi-bit counters and multistage VCOs leads to a much higher resolution than Ref. [6][7].Besides, the behavior of the proposed SMASH ∆Σ ADC is similar to that of a first-order ∆Σ ADC, leading to an improved system stability.The proposed technique can be extended to build more number of stages (1-1-1) or higher order (2-2) VCO-based SMASH ADC.

ADC Architecture
The proposed architecture of the ADC is illustrated in Fig. 1.In this architecture, the input voltage is firstly converted to current signal by the input resistor.After subtracting by the feedback current produced from the current-steering feedback DACs (IDAC), the input current signal of the currentcontrolled oscillators (CCOs) is largely reduced compared with open-loop VCO-based architecture.Instead of using a pair of VCO, a pair of CCOs are used to achieve better linearity.A phase-extended phase/frequency detector (PEPFD) acts as a multi-bit phase quantizer to detect the phase difference between the CCO and the reference phase.For simplicity, the reference phase is assumed to be 0. Different from traditional PFD, the PEPFD uses an extra counter to extend the detection range from 2 to 2 • 2  , where  stands for the number of bits of the counter.The counter counts the number of cycles the CCO leads or lags the reference and serves as the first stage output.The quantization error of the first stage is extracted as the residue phase.This error is fed to a gated-ring oscillator (GRO) based time-to-digital converter (TDC), which works as the second stage and transforms this error from the phase domain to the digital domain [11].The final digital output combines the PEPFD counter output   and TDC output   and then feeds back to the first integrator.The proposed architecture forms a closed loop which makes the signal swing at the CCO input very small, thus it is immune from VCO nonlinearity.The linear signal model of the proposed architecture is shown in.Fig. 2. In this paper, the CCO is treated as a continuous-time (CT) integrator since the upmodulated tones in the CCO's output will be filtered out by the decimation filter, and thus are ignored in the linear model.In this case, The CCO is approximately modeled with a gain of 2 •   •   , where   is the CCO tuning gain and   is the sampling period.Similar to CCO, the GRO is also approximately modeled as a CT integrator with a gain of 2 •   •   , where   is the GRO tuning gain.With an N-stage GRO, the gain of the phase quantizer /.DMSB represents the first stage output as MSB and DLSB represents the first stage output as LSB.Before combining, DLSB is equivalently multiplied by N. The IDAC is modeled with a gain of   .  is the excessive loop delay (ELD) caused by the retiming block.Using the impulse invariance method, the discrete-time (DT) transfer function of the digital output (  ) of the ADC can be derived as: where  = 2        represents the loop gain of the first stage.Equation ( 1) indicates both  1 and  2 are second-order noise shaped as long as   equals to 1/2  .However, in reality,   varies due to PVT variations which may degrade the ADC performance.This issue is addressed by adopting an extra DLL to provide a bias voltage from the control voltage of the voltage-controlled delay line (VCDL) to GRO.This bias voltage ensures GRO running at a fixed frequency to avoid gain mismatch caused by PVT variations [12].The diagram of the proposed architecture is shown in Fig. 3.The input currents are injected into two differential CCOs.Their phase difference is quantized by the PEPFD, which consists of a classic PFD, pulse generators and a multibit up-down counter.The output of this counter is sent to the final output as MSB.The UP and DN signals which represent the phase error are sent to the second stage TDC.

Circuit implementation
Since the residue error is in the time domain, a GRO-based TDC can be directly used to convert the residue.The GRO only needs to process a bi-level waveform, thus it is highly linear and powerefficient.The first register acts as a phase quantizer, while the second register and XOR gate form a digital differentiation, which creates a first-order noise shaping at the second stage.

PEPFD
The schematic of the proposed PEPFD is shown in Fig. 4 and the operating principle of the PEPFD can be further explained in Fig. 5. Starting from  0 , the PEPFD initially operates as a conventional PFD where the phase difference is only represented by signal UP.The running speed of CCOP is much faster than CCON at the beginning.Once the phase difference exceeds the detection range (2π) of the PFD at  1 , the pulse generator creates a pulse (Vgp) which triggers the up-down counter to add one to its output value.When CCOP leads CCON by 2 cycles at  2 , the output turns to be 2 which represents the phase difference is 4.After  2 , the running speed of CCON is set to be much faster than CCOP.Similarly, once the phase difference exceeds the detection range of the PFD at  3 , the pulse generator creates a pulse (Vgn) which triggers the up-down counter to minus one to return its previous output value (DOUTP(t3) = 1).At  4 , the pulse generator creates a pulse (Vgn) to trigger the counter outputting 0 which indicates the phase difference is within −2 and 2, and thus, the PEPFD operates as a conventional PFD during  4 to  5 .The PFD overflows at  5 and the pulse generator creates a pulse (Vgn) to trigger the counter to add one to DOUTN (DOUTN(t5) = 1).Essentially, for every 2 change in the CCOs' phase difference, the counter output will increase or decrease by 1.Therefore, a coarse quantization of the phase can be obtained by counting the PFD overflow.The waveforms generated from the PFD's UP and DN naturally represent the fine residue phase.In this case, the quantization error is extracted in the phase domain with simple digital gates which is power-efficient and scaling-friendly.

Simulation results
The proposed architecture is simulated in Matlab Simulink using a behavioral model with a 4-bit output from PEPFD and a 16-stage GRO.In this design, we assume CCO has 500MHz free-running frequency and gain   = 2000GHz/A.The sampling frequency   is set to be 500MHz.The GRO runs at

Figure 1 .
Figure 1.Architectural block diagram of the proposed ADC.

Figure 2
Figure 2 Linear signal model of the proposed ADC.

Figure 3
Figure 3 Circuit diagram of the proposed ADC.
mismatch of the K CCO (%)