A 111dB-SNDR 20kHz-BW Delta-Sigma Modulator with Auto-Zeroing and Class-AB Amplifier

This paper describes the design of a high-precision audio Delta-Sigma modulator. To guarantee the modulator linearity and resolution with a limited oversampling rate (OSR), 4th-order 1-bit architecture is chosen. Auto-zeroing technique is used to reduce offset and low-frequency noise. To optimize power consumption, the switched-capacitor loop filter is implemented by feedforward structure with a passive adder and class-AB two-stage amplifiers. A clock generator with optimized non-overlapping pulse widths is designed to improve precision. Simulation results in 180nm CMOS show that with a 10.24MHz sampling rate, the presented modulator achieves 111dB signal-to-noise-and-distortion ratio (SNDR) at 20kHz bandwidth (BW) and consumes 17.9mW power under 3.3V supply, corresponding to an excellent figure-of-merit (FoM) of 171.5dB. Simulation results in process corners and temperatures show that the modulator is robust over variations.


Introduction
Nowadays, high-precision analog-to-digital converters (ADCs) are widely used in portable devices such as electric vehicles, mobile phones, and so on.Discrete-time (DT) Delta-Sigma modulators (DSMs) achieve high precision and high energy efficiency in narrowband applications with noise shaping and oversampling techniques.Previously, the modulators based on switched-capacitors (SC) circuit draw great attention since there is no need for employing precision components or stringent matching between constituent elements in design [1].Although switched-capacitance Delta-Sigma ADC publications have declined in recent years, they are still attractive for industrial applications due to their circuit robustness.In recent years, DSMs with different topologies have been proposed for different metrics.Each structure has its advantages and disadvantages.Cascade and multi-bit quantization structures not only need Dynamic Element Matching (DEM) logic to achieve high precision but also increase the circuit complexity [2].Single-bit quantization not only doesn't need DEM logic but also has better linearity than multi-bit quantization.And the circuit of single-loop, single-bit structure is simple and robust.Among different topologies, single-loop, single-bit topology was the first one to be applied to achieve 120dB dynamic range in audio band [3].The feedforward structure is known for better energy efficiency than the feedback one and is widely applied in low-power scenarios.The introduction of the feedforward path allows the loop filter to process only quantization noise, so the design of integrator amplifiers is greatly relaxed, especially for the first stage.The feedforward structure makes a good tradeoff between accuracy and power consumption as in [4].This paper presents a high-precision low-power 4 th -order 1-bit feedforward DT DSM, which is organized as follows.The topology of the proposed DT DSM and its behavioral-level simulated result with circuit nonidealities are shown in section 2. Section 3 shows the detailed circuit implementation of the building blocks of the modulator.In section 4, the simulation results of the modulator circuit are illustrated and the compared results with state-of-the-art works are shown.Finally, conclusions are drawn in section 5.

Modulator Structure
Table 1.presents the relation between the signal-to-noise ratio (SNR) and noise shaping order, OSR for single-loop, single-bit quantizer delta-sigma modulator.To meet design specifications, we choose 4 thorder structure with an OSR of 256.The structure of the proposed delta-sigma modulator is shown in Fig 1 .And Fig 2 .shows the zero and pole plot of the modulator NTF.The four poles are located inside the unit circle to guarantee the stability of the modulator and the four zeros are all positioned at direct current (DC) to provide a good suppression capability for quantization noise.Coefficients of the structure are synthesized by the Matlab SD toolbox, ensuring the modulator stability.By choosing single-bit quantization, the feedback digital-to analog converter (DAC) is intrinsically linear and does not bring any distortion.4 th -order noise shaping reduces the in-band noise to the required level with an OSR of 256, which also show better power efficiency than lower-order ones.The pole and zero plot of the modulator NTF A DSM behavioral model is built in Simulink, including non-idealities such as clock jitter, switched capacitor thermal noise, finite gain, slew rate, and GBW of the amplifiers.And Fig 3 .shows the relationship between the slew rate of amplifier in each integrator and modulator SNDR.Because of single-bit quantization, the quantization error in the modulator loop filter is large, which imposes a stringent requirement on slew rate of first amplifier, as indicated in Fig 3 .In Fig 4, the behavioral-level simulated power spectral density (PSD) of the DSM is presented, with an input amplitude of -3.1dBFS, the modulator achieves a peak SNDR of 114.2dB.Through the behavioral model, the coefficients of the structure, the performance requirements of the amplifiers, and the size of capacitance can be optimized.shows the whole delta-sigma modulator circuit.The timing of the switched capacitors is controlled by two phase non-overlapping clock.Bottom plate sampling technique is used to reduce nonidealities such as nonlinearity, which is mainly caused by charge injection during sampling.The nonideal amplifiers in integrators will directly degrade the final performance of the whole modulator, especially the amplifier in the first integrator.To reduce these nonidealities, a non-overlapping clock generator with different pulse widths is designed and used.The longer integrated time, the lower design specifications for each stage amplifier to set up.Due to the use of single-bit quantization, the signal input to the first-stage integrator is large, resulting in high requirement for the first-stage amplifier, so a class-AB two-stage amplifier with miller compensation is designed and used in this modulator.Since the frequency of input signal can be as low as 20Hz, the modulator performance is also sensitive to offset and flick noise of the first stage.To reduce these low frequency nonidealities, auto-zeroing technique is applied in this high-precision modulator.As is shown in Fig. 5, during sampling phase, the first stage amplifier is connected as unity-gain negative feedback and two auto-zeroing capacitances C Z are connected to its inputs in order to store the offset and low-frequency noise.During integration phase, the voltage of the auto-zeroing capacitances is subtracted from the input of the amplifier, thereby the offset and low frequency noise are reduced.In addition, a large sampling capacitance in the first stage allows the thermal noise to meet design requirements.

Bootstrapped Sampling Switch
In DT DSMs, using simple CMOS switches will result the on-resistance of the switches varying with different amplitude of input signal during the sampling phase, and this can result nonlinearity in the sampling network.The nonlinearity of the front-end sampling switch is always the bottleneck of modulator performance.To mitigate this distortion, a bootstrapped switch is used in the input of the first integrator to guarantee constant over-driver voltage for the switch transistor, ensuring almost constant on-resistance with the varied input voltage, as shown in Fig 6 .The value of on-resistance is given by: In the sampling phase, bottom plate sampling also helps to reduce sampling non-idealities such as clock feedthrough and charge injection.

Amplifier Circuit
Wherever In order to achieve high accuracy, a large sampling capacitance needs to be used in the first integrator, leading to a large load of the first integrator amplifier, calling for high amplifier slew rate.In behavioral simulation, DC gain of 60dB, gain bandwidth product (GBW) of 60MHz, and slew rate of 60V/uS are required for the amplifier in the first integrator to keep modulator performance degradation low enough.In this design, a power-efficient two-stage miller-compensated amplifier with class-AB output stage is adopted.Fig 7 .shows the detailed transistor circuit of this proposed amplifier.The amplifier combines a simple differential pair of the first stage and the second stage through a current mirror.Due to the class AB operation in the second stage, slew rate limiting only occurs in the first stage.And the output branch current can be about half that used in the two-stage class A circuit for the same non-dominant pole frequency.The amplifier slew rate is given by: where I 1 is the bias current in the first stage.The common-mode feedback loop chooses a switchedcapacitance feedback one, not only ensuring the stability of the amplifier circuit but also reducing the load of the circuit.Since the modulator thermal noise is mainly contributed by the sampling network and the amplifier in the first integrator.Noise of a two-stage miller-compensated amplifier is approximately given by: where C c is the two-stage amplifier miller compensation capacitor, and γ is the noise enhancement factor of short channel transistors.C s and C I are sampling and integration capacitors.g m1 and g m3 are the transconductances of the input transistor and load transistor, respectively.To reduce the flick noise of the amplifier at low frequency, PMOS is used as the input differential pair, furthermore, the transistor sizes of the input pair and the current bias are set large enough to meet the flick noise requirements [5].Simulation results show that the designed amplifier in first integrator achieves 83.3dB gain, 75.6MHzGBW, and 62.1º phase margin, and consumes 8.86mW power consumption under 20pF capacitive load, as is shown in table 2.
It can be seen that due to the parasitic capacitance C p , the ratio of C 1 and C 2 to C p must be large enough to reduce the nonideal characteristics.

Dynamic Latch Comparator
The comparator of this proposed Delta-Sigma modulator is a single-bit dynamic latch one, with no static power consumed during the reset phase.In the comparison phase, the correct comparison voltage is obtained after pre-amplification and latching.Then an SR latch holds the comparison result to generate the single-bit digital output code, and the code is further used as the control signal of the reference voltage for the feedback CDAC.

Clock Generator
Switched-capacitance DSM requires several clock signals with different phases to control building blocks, which is generated by a non-overlapping clock generator circuit.Because sampling and integration phase require different sufficient time to achieve the requested accuracy, the designed clock generator can control the width of the two-phase pulses by setting different delays.About 10% width is borrowed from φ 1 to the φ 2 phase to ensure sufficient settling in integration phase.This timing scheme can reduce the design specifications of the amplifier, and improve the efficiency of the modulator.In this design, the pulse width and the delay time can also be adjusted by controlling digital gates with capacitive load.

Simulation Results and Discussion
The presented modulator is designed and simulated in 180nm CMOS.Fig 9 .shows the transistor-level simulated PSD of the presented modulator with 65536 sampling points, where transient noise is included.
It can be seen that with a -3.5dBFS amplitude and 2.03125KHz frequency input sinusoidal signal, the modulator can achieve a peak SNR of 110.3dB and a peak SNDR of 106.5dB, resulting in a 167.1dBFoM without using the auto-zeroing technique.For comparison, the modulator can achieve a peak SNR of 112.8dB and a peak SNDR of 110.9dB with auto-zeroing technique under the same condition.By using auto-zeroing technique, the SNDR of the modulator has a 4.4dB promotion, and its SNDR also has an improvement of 2.5dB.

Conclusion
In this paper, a 4 th -order 1-bit feedforward DT DSM has been shown.Auto-zeroing technique is used in the first integrator to reduce offset and low frequency noise.A passive adder and a class-AB amplifier are adopted to reduce power consumption without sacrificing the performance of the modulator.To ensure sufficient settling time for the integrator, a non-overlapping clock generator with different width phases was designed.Simulated in 180nm CMOS, the proposed modulator achieves 111dB peak SNDR in 20kHz BW, with a 10.24MHz sampling clock.The modulator consumes about 17.9mW power from 3.3V supplies, with a competitive FoM of 171.5dB.With lower nanometer technologies and lower supply voltage, future power improvement can be made, taking benefits of digital part.And power can also be optimized in analog part by using novel amplifiers, such as dynamic amplifiers.

Fig 1 .
Fig 1. Overall structure of the proposed DSM

Fig 4 .
Fig 4. Behavioral-level simulation result of the DSM3.Circuit ImplementationFig 5.  shows the whole delta-sigma modulator circuit.The timing of the switched capacitors is controlled by two phase non-overlapping clock.Bottom plate sampling technique is used to reduce nonidealities such as nonlinearity, which is mainly caused by charge injection during sampling.The nonideal amplifiers in integrators will directly degrade the final performance of the whole modulator, especially the amplifier in the first integrator.To reduce these nonidealities, a non-overlapping clock generator with different pulse widths is designed and used.The longer integrated time, the lower design specifications for each stage amplifier to set up.Due to the use of single-bit quantization, the signal input to the first-stage integrator is large, resulting in high requirement for the first-stage amplifier, so a class-AB two-stage amplifier with miller compensation is designed and used in this modulator.Since the frequency of input signal can be as low as 20Hz, the modulator performance is also sensitive to offset and flick noise of the first stage.To reduce these low frequency nonidealities, auto-zeroing technique is applied in this high-precision modulator.As is shown in Fig.5, during sampling phase, the

Fig 5 .
Fig 5. Circuit of the proposed Delta-Sigma modulator

Fig 6 .
Fig 6.Schematic of the bootstrapped switch

Fig 7 .
Fig 7. Circuit of the proposed Class-AB amplifier

Fig 8 .
Fig 8. Circuit of the passive adder

Fig 9 .
Fig 9. Simulated PSD of the modulator circuit with/without auto-zeroing

Table 1 .
SNR as function of OSR and noise shaping order 3 Fig 3. Modulator SNDR as a function of the amplifier Slew Rate

Table 2 .
Simulation results of amplifiers To reduce power consumption, the adder in the feedforward modulator is a passive one.Because the DSM uses a single-bit quantizer with undefined gain, the gain attenuation brought by the passive adder does not degrade the modulator performance.The schematic of the passive adder is shown in Fig 8, φ 1 makes a summation function by charge redistribution, φ 2 is a reset phase, and C p holds the previous voltage V o ′ .Its transfer function in two phases can be given by

Table 3 .
also gives simulation results of the modulator under different PVTs, and it can be observed that the modulator is very stable under different conditions.The entire DSM consumes 5.42mA current from 3.3V analog and digital supplies, resulting into an excellent FoM of 171.5dB, and its detailed power distribution is shown in Fig 10.It can be seen that the analog part consumes about 81% of the whole power consumption.And the digital part only consumes 19%.Table4.summarizes the modulator performance and compares it to state-of-the-art designs, our design reaches the best accuracy performance with comparable FoM.

Table 3 .
Simulation results with PVT Fig 10.Power distribution of the DSM

Table 4 .
Performance summary and comparison