TCAD Simulation of X-ray irradiated Si microstrip detector : Impact on full depletion voltage and leakage current

In the intense x-ray radiation environment at synchrotron sources, it is reported that the performance of the silicon pixel detectors degrades with an increasing x-ray dose up to 10 MGy. To study the impact of x-ray irradiation effects in the n-Fz Si microstrip detector, the microscopic radiation damage parameters of x-ray radiation were extracted from the current–voltage, and capacitance-voltage experiments on test Si microstrip detector. The damage parameters are implemented in Synopsys TCAD. In this paper, we have irradiated the test structure up to 10 MGy, and the results on full depletion voltage, and leakage current are compared with the TCAD simulation results. A very good agreement in between experimental and simulation results is observed in the leakage current for the non-irradiated, and 1 MGy irradiated detectors, where for high doses up to 10 MGy, experimental leakage current was fifty times higher than the simulated leakage current at full depletion voltage. The full depletion voltage in 0 MGy detector is also well matched with the simulation result, and further, it shows the full depletion voltage performance of x-ray irradiated detector. Finally, the new detector design specifications and process parameters are proposed for the optimum performance of the radiation hard p+n Si pixel detector equipped with guard rigs at cut edge for the next generation photon science applications.


Introduction
Science at synchrotron facilities requires an incredible silicon p + n pixel detector, that can efficiently operate in the harsh radiation environment.It has been reported in several literature, that the detector at these facilities have to withstand the x-ray dose of 1GGy of energy >10 keV for the smooth operation of the experiments [1][2][3][4][5].
The intense x-ray radiation deteriorates the Si detector performance by inducing the fixed oxide charges (Nox) and interface trap charges (Nit) in the insulating layer and at Si-SiO2 interface respectively [2,6] and these charges increases with an increasing x-ray dose and finally, saturates at few MGy of x-ray dose [6,8].These radiation damage parameters changes the macroscopic performance of the the detector by increasing full depletion voltage (Vfd), surface leakage current, inter strip capacitance, reduction of breakdown voltage and charge lose at the interface of the detector.
In order to understand the surface radiation damage on Si detector performance, the p + n Fz Si microstrip test structure has been irradiated by a x-ray dose upto 10 MGy of energy 10 keV at F4 beam of DESY DORIS III synchrotron source [5].The electrical performance has been characterized for irradiated and non-irradiated test structure by Hamburg group, Germany.
In this present work, the x-ray induced microscopic radiation damage parameter extracted from gate controlled devices (GCD) and metal oxide semiconductor (MOS) capacitors are sufficiently tuned and implemented in Synopsys Technology Computer Aided Device simulation (TCAD) simulator, to reproduce the experimental data on Vfd and leakage current for irradiated and non-irradiated p + n Fz Si microstrip detector.Finally, the new guard ring design layout and process and device parameters are proposed for the optimum performance of Si p + n pixel detectors at synchrotron sources.

Detector structure
The detector structure used in the present study was manufactured on nFz silicon substrate with orientation <100> by CiS, Germany.The detector model consists of an AC coupled p + n Si microstrip test structure of (0.643 cm 2 x 282 µm) dimension, having an n-type Si substrate with a uniform doping concentration (Nd )of 8.1 × 10 11 cm −3 .The gap between the adjacent p + strip is 62 µm and the pitch of the strip is 80 µm.The oxide and nitride thickness between the aluminium strips denoted by tox is (300 nm + 50 nm) and the oxide and nitride thickness between p + implant and aluminium strip denoted by tcp is (100 nm + 50 nm).The extension of metal (Wmo) over the oxide is 2 µm.The irradiation campaign on this Si microstrip test structure was carried out at F4 beam line of DESY DORIS III [4][5].Our group leader along with the Hamburg group, Germany has measured the current/voltage (I-V) and capacitance/voltage (C/V) characteristics at 293 K at 100 KHz for a x-ray dose of 0, 1 and 10 MGy.
The cross section of an AC coupled p + n Si microstrip detector implemented in TCAD device simulation is shown in figure 1.

TCAD Device Simulation and Radiation Damage Modelling
Technology computer aided device simulator tool offers the variety of approaches for the static and dynamic analysis of semiconductor devices.In the present work, device geometry shown in figure 1 is defined in Synopsys TCAD [7].The device simulation is performed at 293 K and to examine the real behaviour of the detector under the radiation influence, physical models such as schokley Read Hall (SRH) recombination model, impact ionization model from van Overstraeten -de Man, band to band tunneling and drift diffusion mobility model were switched on.Neumann boundary condition was used at the top of oxide and Dirichlet boundary condition was applied at the boundaries of the detector for the entire simulation.
The behaviour of p + n Si microstrip detector after the x-ray irradiation is simulated using the microscopic radiation damage parameters as a first step is shown in table 1.The simulation is carried out for non-irradiated and irradiated test structure with an x-ray doses of 0,1 and 10 MGy.The uniform distribution layer of Nox = 2.08 x 10 12 cm -2 (for 1 MGy X-ray dose ) and Nox = 2 x 10 12 cm -2 (for 10 MGy X-ray dose ) [5] and the corresponding Nit were implemented at the interface of the detector for the surface damage analysis.

Table 1.
Two interface deep trap level model, providing energy level positioning, rms width σit (eV) and interface trap density (Dit cm -2 eV) for an x-ray dose of 1 and 10 MGy are implemented in TCAD simulation [5].
The capture cross-sections of both interface trap eff= 2.75 x 10 -15 cm 2 is sufficiently tune for good agreement in experiment and simulation data.

Simulation Results and Discussion
The 2D numerical analysis of C-V (Vfd) and leakage current in x-ray-irradiated Si microstrip detector is investigated in detail.TCAD simulations were performed to compare the simulation results and the experimental data for the different x-ray doses.

Impact of x-ray dose on full depletion voltage
To calculate the Vfd of irradiated and non-irradiated detector the C-V characteristics has been simulated at an applied bias of 100 V at 100 KHz frequency and no interface traps were considered in the simulation.In order to check the accuracy of the simulator, the simulation results are being verified with the analytic calculations on Vfd and Cj for p + n Si microstrip detector (excluding Nox and Nit ).
The full depletion voltage for non-irradiated p + n Si microstrip test structure can be analytically calculated using ,here Nd is the doping concentration, ∈Si is the dielectric permittivity of silicon.
The calculated value of Vfd for the Nd=8.1 x 10 11 cm -3 and Wn = 282 µm is 49.76 V which is in 20 % uncertainty with the experimental value.The geometrical capacitance (Cj) at Vfd can be calculated using The measured value of Cj at Vfd is 23.6 pf .Capacitance as a function of applied bias voltage for an xray dose of 0, 1 and 10 MGy is shown in figure 2

Impact of x-ray dose on leakage Current
The p + n Si microstrip test structure was irradiated with an x-ray dose of 0, 1 and 10 MGy and the corresponding radiation damage parameters were implemented in simulation to simulate the I-V characteristics at an applied bias of 100 V. Figure 3 shows the the leakage current as a function of applied bias voltage of the irradiated and non-irradiated detector.Hence, it can be conclude that surface leakage current increases due to Interface charge carrier density trapped in this non implanted depleted surface area.

Optimized Guard ring layout of Silicon p+n pixel detector design
To meet the challenging requirement of p + n Si pixel detector for the synchrotron applications, aforesaid study have been carried out by implementing the microscopic radiation damage model in TCAD simulation.It has been found that electrical performance of the detector degrades with an increased x-ray doses and hence, to meet the specification of the experiments the optimized p + n Si inner pixel and guard ring design is the utmost requirement.The novel design option with optimized detector performance like high breakdown voltage (Vbd) and CCE is reported in [4,10].It has been found that using the design parameter shown in table 2 the Vbd of 750 V and high CCE is achieved for the synchrotron application.However, it has been claimed in several literature that, for heavily x-ray irradiated detector the optimized guard ring layout is required to increase the Vbd >1000 V and high CCE.
Here, based on the detector specification for experiments like Eu-XFEL and our simulation studies, the outer pixel guard ring layout having the dead edge of 620 µm with intra guard ring (IGR) and wide guard ring (WGR) technology near to the cut edge is proposed to achieve the Vbd> 1000 V and high CCE as discussed [10] and the schematic of layout design and its parameter is shown in figure 5 and table 2. As expected from the previous analysis, the Vfd for 10 MGy irradiated detector will be around 137 V with 20% uncertainty for Nd of 1 x 10 12 cm -3 .

Conclusion
In this work, we have aimed to reproduce the experimental results on full depletion voltage and leakage current in x-ray irradiated p + n Si pixel detector using TCAD device simulation.Here, the xray dose dependent microscopic damage parameters equivalent to 0,1, and 10 MGy are implemented in Synopsys TCAD device simulation program to simulate the I-V and C-V characteristics of the p + n Fz Si microstrip test structure.A very good agreement of simulation results and experimental results are obtained on Vfd for 0 MGy.It has been found that full depletion voltage increase from 60 V to 70 V with an increasing x-ray dose of 0 to 10 MGy.The leakage current results also well matched at 0 and 1 MGy where for high doses up to 10 MGy, experimental leakage current was fifty times higher than the simulated leakage current at full depletion voltage.It is concluded that x-ray induced radiation damage microscopic parameters degrades the electrical performance of the detector.Finally, based on several literature review and our simulation analysis outer pixel guard ring layout with wide guard ring technology at the cut edge is proposed to achieve the Vbd>1000V and high CCE as expected for next generation photon science experiment.

Figure 1 .
Figure 1.Cross section of an AC coupled p + n Si microstrip detector implemented in TCAD device simulation.

Figure 2 .
Figure 2. (a) 1/ C 2 as a function of applied bias voltage for an x-ray dose of 0, 1 and 10 MGy, (b) full depletion voltage as a function of device thickness.

Figure 3 .
Figure 3. Leakage current as a function of applied bias voltage for an x-ray dose of 0, 1 and 10 MGy.It can be seen from the figure3that the simulation results are in good agreement with the experimental results for 0 and 1MGy x-ray dose .Leakage current increases with an increasing x-ray dose and does not shows any saturation at Vfd.It is due to the interface trap (Nit) formed in the depletion region near interface (Sdep) however, Nox in oxide region leads to the formation of electron accumulation layer within the 100 nm region from the Si-SiO2 interface and the electric field in this region is very low.Therefore, Nit contributes to the surface leakage current (Isurf) which is the dominant leakage current in x-ray irradiated detector.The non implanted depleted surface area near interface increases with an increasing biased voltage as shown in figure4.

Figure 4 .
Figure 4. Interface depleted area as a function of applied bias voltage.

Figure 5 .
Figure 5. Cross-section of outer pixel guard ring layout for p + n Si pixel detector.

Table 2 .
Device and process parameter of outer pixel guard ring layout.