Multi-channel and high-precision analog-to-digital converter chips for power grid detection

This project focuses on the research of high-precision multi-channel analog-to-digital converter chips for power grid detection and system applications. There have been breakthroughs made in a series of key technologies, such as successive approximation ADC architecture, oversampling ADC architecture, and digital calibration technology. By combining it with multi-channel ADC to achieve high-precision multi-channel analog-to-digital converter design, it provides strong support for China to achieve autonomous and controllable high-precision multi-channel ADC chips and has extremely high application value.


INTRODUCTION
With the rapid development and upgrading of modern power grid systems, the demand for power transmission and distribution networks in the power grid is increasing, promoting the rapid development of intelligent substation comprehensive automation technology as an important support for power grid operation [1] .With the increase in labor costs and the development of microprocessor technology, adopting high-precision automatic control systems to achieve automated power grid detection and control has become an inevitable choice for power industry systems, saving costs for management and equipment control in the power sector. Figure 1 is a typical power safety monitoring system that utilizes an external voltage or current sensing network to continuously sample signals within a cycle.It calculates their effective values through multiple sampled data.Then, the data processing circuit DSP is used to complete the multi-channel synchronous conversion and measurement operation of the AD signal [2] .The results of the calculation are simultaneously transmitted through the serial port to the microcontroller for data storage and display control, and ultimately displayed in the LCD display module with the required information.The power supply quality management system detects the voltage and current of the multiphase power grid while monitoring and detecting the frequency harmonics of the load.The measurement accuracy of power monitoring in the power grid system is achieved through a synchronous sampling of high-precision ADC [3] .As shown in Figure 2, in a typical three-phase measurement system, after obtaining the three-phase current and voltage signals from three current transformers (CT) and voltage transformers (PT), the ADC needs to perform synchronous sampling on each channel after signal conditioning processes such as filtering and buffering [4][5] .Due to the typical transformer output generally being within ± 620 mV, high-precision ADC is required to achieve multi-channel synchronous sampling for accurate measurement of small signals.In addition, the measurement of power system current also puts forward high requirements for the dynamic range of ADC.Therefore, the research on high-precision multi-channel analog-to-digital converter chips has a high value in the field of power grid detection and system applications.

DESIGN AND IMPLEMENTATION
This design proposes a novel multi-channel sampling ADC that uses a successive approximation method to perform analog-to-digital conversion of input signals.This design reconstructs the sample structure, the hold circuit, and the comparison conversion circuit in SAR ADC [6] .By adding capacitance in each sample and hold circuit, each sample and hold circuit not only samples the input signal but also converts the input signal.Due to the analog-to-digital conversion of the signal before entering the original capacitor array in this method, when the sampling and holding circuit are connected to the capacitor array, only the quantization margin is used for charge sharing, greatly reducing the signal attenuation.Compared with previous schemes, the proposed scheme of the present invention can improve the signalto-noise ratio under the same power consumption or area, thereby improving the accuracy of ADC.It is a new architecture for achieving high-precision multi-channel sampling ADC.

Design of a Novel Multichannel Synchronous Sampling ADC Architecture
Figure 3 shows a schematic diagram of the new multi-channel sampling ADC architecture.The capacitor array C 1i (i=1 to N) first samples the analog input signal Vin i of the corresponding channel simultaneously and then sequentially closes S 11 -S 1N to perform analog-to-digital conversion on the sampled values of each channel [7] .The conversion process of each channel can be divided into two conversion processes.The first channel is taken as an example.First, C 11 , comparator, and logic circuit form a SAR ADC for the first conversion.The final ADC output (one bit or the first few bits) is the most significant bit (MSB).Next, the shared capacitor array C 2 is connected to the comparator through the control of switch S 2 .After obtaining the voltage difference of the previous conversion, a second conversion is performed, and the output (one or the last few bits) obtained is the Least Significant Bit (LSB).By combining the first few (or one-bit) MSBs and the last few (or one-bit) LSBs together, all digital outputs of the channel are obtained.If the ADC has a total of N input channels, this process needs to be carried out N times in sequence, and the ADC converts the analog input signals of the N channels into the final digital output.The multi-channel ADC architecture proposed in this design enables each sampling and holding circuit to not only sample the input signal but also perform analog-to-digital conversion on the input signal [8] .Due to the analog-to-digital conversion of the input signal of this method before entering the original capacitor array, only the quantization margin is used for charge sharing when connecting the sampling and holding circuit to the shared capacitor array, greatly reducing the attenuation of the signal.Compared with previous work, the ADC architecture proposed in this design can improve the signal-tonoise ratio under the same power consumption index, thereby improving the accuracy and energy efficiency of the ADC.

Correction Algorithm in Multi-channel Synchronous Sampling ADC
For the new multi-channel synchronous sampling ADC architecture mentioned above, due to layout asymmetry and process mismatch, there are mismatch errors between the channels of the multi-channel synchronous sampling ADC, and the performance cannot achieve the ideal state.Therefore, it is necessary to calibrate multi-channel synchronous sampling ADCs to reduce mismatch errors between channels and improve the performance of multi-channel synchronous sampling ADCs [9] .The errors between channels mainly include offset mismatch, gain mismatch and sampling mismatch.Digital background calibration uses the statistical rules of digital codes to calibrate channel mismatches in the digital domain without interrupting the working state of the ADC or introducing additional analog circuits in the system.It has a wide range of applications and good process adaptability, making it a current research hotspot.Therefore, this article uses digital background calibration technology to calibrate the mismatch errors of each channel in the multi-channel synchronous sampling ADC architecture.The basic idea is to eliminate the relative mismatch error between channels by using the first channel as the reference channel and approaching other channels towards the reference channel.Below is a detailed explanation of the calibration method for channel mismatch.

1) Misalignment calibration
The calibration of channel misalignment and mismatch generally adopts the cumulative average method, and the basic principle is introduced below.Assuming that the offset error and gain error of ADC are  and , respectively, the output of ADC can be expressed as: X a x V V Equation 1 where  and  represent the AC and DC components of the input signal, respectively.After averaging the output signal, the output DC component  can be obtained: A mean X aV V . 2 According to Equation 2, if the input signal has a DC component, the offset of the ADC cannot be distinguished from the DC component of the input signal.However, for multi-channel time-domain interleaved ADC, as long as the gain error of each channel is the same, the relative offset error between channels can be extracted.Assuming the first channel is used as the reference channel, the offset error of the i-th channel relative to the first channel can be expressed as: Equation 3 Figure 4 illustrates the method of using the cumulative average method to eliminate inter-channel mismatch.The specific working process is as follows: first, each channel estimates its own DC component by accumulating and averaging its digital output code.Then, the DC component of the i-th channel is subtracted from the DC component of the 1st channel to determine the relative misalignment between these two channels.Finally, this offset voltage is subtracted from the output code of the i-th channel to eliminate the relative offset between the i-th channel and the first channel.2) Gain mismatch calibration The calibration of channel gain mismatch is also very simple, usually using the cumulative average method.The basic principle of this method will be introduced below.Assuming that the input signal has no DC component and the ADC has no offset error, the mean of the absolute value of the ADC output can be obtained as:

ΔA osi
||  || ||.Equation 4 According to Equation 4, the gain error cannot still be extracted, but similar to offset mismatch, the relative gain error between the two channels can be obtained through division operation.If the first channel is used as the reference channel, the relative gain mismatch between the i-th channel and the first channel can be expressed as: ∆A .Equation 5 Figure 5 illustrates the cumulative average method to eliminate the gain mismatch between channels [10] .The specific working process is as follows: first, after taking the absolute value of the digital output code of each channel, the average amplitude of each channel is estimated through the cumulative average.Then, the average amplitude of the first channel is divided by the average amplitude of the i-th channel to extract the relative gain mismatch of the i-th channel relative to the first channel.Finally, multiplying the output code of the i-th channel by the extracted relative gain mismatch can eliminate the relative gain mismatch between the i-th channel and the first channel.
According to the analysis above, the premise of using the cumulative average method to calibrate gain mismatch is that there is no DC offset.The premise of using the cumulative average method to calibrate offset mismatch is that there is no gain mismatch.Therefore, to calibrate these two types of errors, the DC offset must be removed before the gain mismatch can be calibrated, and finally, the DC offset can be added back.The specific work process can be divided into three steps: Step 1: DC elimination: Each channel extracts its own output DC component by accumulating the average output code and then subtracting the extracted DC offset from the output code of each channel.
Step 2: Gain mismatch calibration: By using the gain mismatch accumulation average calibration method introduced earlier, the gain error of all channels is approximated to the gain error of the first channel.
Step 3: DC restoration: The output DC component extracted from the first channel is added to the digital codes of each channel that have undergone gain mismatch calibration.In practical applications, if the input signal does not have a DC component, the third step can be omitted.

CONCLUSION
Traditional multi-channel synchronous sampling ADCs generally use multiple ADCs for conversion or use multiple sampling and holding circuits for sampling before conversion.Table 2 shows the technical specifications of the ADC.These two circuit architectures have drawbacks such as high noise power consumption and large chip area occupation.This project proposes a new multi-channel sampling ADC, which not only samples the input signal but also converts it by adding capacitors to each sampling and holding circuit.This architecture significantly reduces signal attenuation and achieves innovation in architecture.

Figure 1 .
Figure 1.Schematic diagram of a typical power safety monitoring system

Figure 2 .
Figure 2. Schematic diagram of a typical three-phase measurement system

Figure 3 .
Figure 3. Schematic diagram of the new multi-channel sampling ADC architecture

Figure 4 .
Figure 4. Mismatch and mismatch accumulated average calibration method

Figure 5 .
Figure 5. Offset mismatch and gain mismatch cumulative average calibration method

Table 1 .
The simulation results (dB)

Table 2 .
Technical indicators