A High Crosstalk Suppression SiC MOSFET Gate Driver

Fast switching speeds and high switching frequencies bring serious crosstalk problems in SiC MOSFET applications. In this paper, we design a SiC MOSFET gate driver with high crosstalk suppression capability by using a multi-level drive and active Miller clamp technology. In the design, an auxiliary branch is introduced to control the source potential of the SiC MOSFET to achieve multilevel driving. The branch has a simple structure, simple control logic, no external negative voltage supply, and adjustable negative output voltage. The proposed SiC MOSFET gate driver was designed using the Central Semiconductor Manufacturing Corporation (CSMC) 0.8 μm BCD high voltage process. The designed SiC MOSFET gate driver has an area of 2967 μm × 3180 μm. The simulation verification model is based on Wolfspeed’s SiC MOSFET product C3M0075120D. Post-layout simulation results show that a SiC MOSFET gate driver with a crosstalk suppression capability of over 150 V/ns is obtained, which can reliably drive SiC MOSFET power devices.


Introduction
SiC MOSFETs are utilized extensively in the production of new energy generation and electric vehicles due to their superior material properties, such as large forbidden bandwidth, high breakdown field strength, and good heat dissipation, which enable them to work better under higher frequency and higher power density conditions [1].However, the quick switching speed and high switching frequency will result in huge dv/dt and di/dt during SiC MOSFETs' turn-on and turn-off, which can cause severe current-voltage spikes, oscillations, and crosstalk problems at the gate under the influence of circuit parasitic parameters [2], and thus can result in additional losses during switching and false turn-on of SiC MOSFETs at turn-off period, or even a device breakdown [3].
The crosstalk issue has become a significant element influencing the reliability of SiC MOSFETs [4].For improving crosstalk suppression, the following methods are available.In [5], the crosstalk voltage suppression is achieved by connecting large capacitors in parallel between the SiC MOSFET gate and source, thus reducing the parasitic impedance between SiC MOSFET gate and source, but this will reduce the SiC MOSFETs' switching speed and increases power losses during switching.Optimizing the PCB architecture and lowering the parasitic parameters can reduce crosstalk, but the effect is constrained by the package structure, cost, and power factors [6].In [7], crosstalk suppression is achieved by slowing down the switching speed of SiC MOSFETs using buffer circuits and larger gate resistors, but the device advantages of SiC MOSFETs cannot be fully exploited, and the switching losses are increased.In [8], a negative voltage was used to turn off SiC MOSFETs, which can suppress positive gate-source crosstalk voltage, however, it cannot suppress negative gate-source crosstalk voltage.Under the influence of the negative crosstalk voltage, the negative voltage of the SiC MOSFET gate intensifies, which may lead to the SiC MOSFETs breakdown.Negative voltage and zero voltage were used for SiC 2 MOSFET turn-off in [9], the negative voltage is used when the positive crosstalk voltage is present, while the zero voltage is used when the negative crosstalk voltage is present.In this way, the positive and negative crosstalk voltage suppression of the SiC MOSFET is achieved, but the control logic is complex and requires the provision of multilevel control signals.
This paper presents a SiC MOSFET gate driver that uses a multi-level drive and active Miller clamp technique to achieve high crosstalk suppression.The multi-level drive function is realized by introducing an auxiliary branch to control the SiC MOSFET source potential.The circuit has a simple structure and simple control logic and does not require an external negative voltage supply and adjustable negative output voltage.Active Miller clamp technology is used to further improve the crosstalk suppression capability.Section II presents the mechanism causing the bridge arm crosstalk phenomena and analyzes the elements affecting the crosstalk voltage.The proposed gate driver is introduced in section III, and its basic workings are analyzed.In section IV, the designed gate driver is simulated, and the simulation results are analyzed.The conclusions reached are set out in section V.

Generation of the crosstalk
The SiC MOSFET half-bridge application is used for the analysis of the causation mechanism of the crosstalk phenomenon.Figure 1 depicts the equivalent circuit diagram of SiC MOSFET half-bridge application, where Q L is the low-side power transistor, Q H is the high-side power transistor, V GS_H and V GS_L are Q H and Q L gate-source voltages, respectively, R GEX_H and R GEX_L are Q H and Q L external gate resistors, respectively, R GINT is the SiC MOSFET gate internal resistance, R Driver_H , and R Driver_L are t Q H and Q L gate driver internal resistance, respectively, L S1_H and L S1_L are the gate parasitic inductances of Q H and Q L , L S2_H and L S2_L are the source parasitic inductances of Q H and Q L , respectively, C GD_H and C GD_L are the gate-drain parasitic capacitances of Q H and Q L , C GS_H and C GS_L are the gate-source parasitic capacitances of Q H and Q L , respectively.During Q H turns on, Q L exhibits a change in its drain-source voltage from zero up to V DS .The Miller current is generated due to rapid changes in the drain voltage of Q L , which flows to the ground through the gatedrain parasitic capacitor C GD_L and SiC MOSFET gate resistor, resulting in a positive crosstalk voltage at the low side power transistor gate.The equivalent circuit when Q H is turned off and Q L in an off state is shown in Figure 1(b).Before Q H is turned off, the voltage between the drain and the source of QL is close to V DS .After Q H is turned off, the Q L drain-source voltage drops to zero, and the low-side power transistor gate will produce a negative crosstalk voltage.Figure 2 shows the low-side power transistor's gate-source voltage with negative turn-off voltage when crosstalk occurs.It is clear that if a large positive crosstalk voltage is generated when the high-side power transistor is turned on, it may cause the low-side power transistor to mislead and cause the bridge arm to pass through.When the high-side power transistor is turned off, if a large negative crosstalk voltage is generated, it may cause a negative voltage breakdown of the low-side power transistor.

Factors influencing crosstalk voltage
In this paper, an equivalent circuit of the low-side power transistor in the half-bridge circuit is constructed to analyze the influence of significant parasitic parameters on the crosstalk voltage, as shown in Figure 3.Where V EE is the gate-source voltage when the low-side power transistor is turned off, R g is the low-side power transistor gate equivalent resistance, and its value is the sum of the lowside power transistor gate driver internal resistance R Driver_L , low-side power transistor gate external resistance R GEX_L , and low-side power transistor gate internal resistance R It can be seen that the crosstalk voltage magnitude is intimately connected to the power tube turn-off voltage V EE , the gate resistor R g , the gate inductor L s1 , the gate input capacitance C iss , and the rate of drain-source voltage change.As illustrated in Figure 4, a double-pulse test circuit is designed to examine the influence of different parasitic factors on the crosstalk voltage.The SiC MOSFET model uses Wolfspeed's C3M0075120D [10], and its device parameters are shown in Table 1.When the external gate resistance is 2 Ω, the crosstalk voltage will cause the SiC MOSFET to turn on incorrectly.The effect of the external gate resistance on the negative crosstalk voltage is shown in Figure 5(b).The larger the gate resistance is, the larger the absolute value of the negative voltage is. Figure 6 shows the effect of different external gate resistances on crosstalk voltages for the negative-voltage turn-off case.The crosstalk voltage shifts down overall compared to zero voltage turnoff.Under the same operating conditions, negative voltage turn-off can improve the crosstalk suppression capability of the SiC MOSFET.It should be noted, however, that when negative voltage turn-off is used, the negative spike will intensify the negative gate-source voltage, which can result in negative voltage breakdown of the SiC MOSFET.To confirm the impact of the gate-source capacitance on the crosstalk voltage, various-sized capacitors are connected in parallel between the SiC MOSFET gate-sources.The simulation results are illustrated in Figure 7, which indicates that the absolute crosstalk voltage is negatively correlated with the gate capacitance.Increasing the gate capacitance can reduce the effect of crosstalk, but it also slows down the switching process of the SiC MOSFET.The pull-up chain and the pull-down chain form a conventional gate driver.The Miller clamp chain enables a low impedance path for Miller current after SiC MOSFET turn-off, improving the crosstalk suppression capability of the circuit.The multi-level driver generation circuit consists of a Schmitt trigger, delay module Delay_S, S1 Control module, capacitor C1 charging boost module, switch S1, regulator Z1, capacitor C1, and resistor R1.The on-state resistance of switch S1 is much smaller than that of resistor R1.The capacitor C1 charging boost module is used to accelerate the charging speed of capacitor C1.The S1 Control module is used to control the turn-on and turn-off of the switch S1, which can adjust the source potential of the SiC MOSFET to achieve multi-level drive.The complete control period of S1 is shown in Figure 9. Based on the control timing of S1, the operation of the multi-level driver generation circuit is analyzed as follows.

Simulation
The gate driver proposed in this paper was designed based on Central Semiconductor Manufacturing Corporation (CSMC) 0.8 μm BCD high voltage process platform.The gate driver layout is shown in Figure 10, which has an area of 2967 μm×3180 μm.The position of each module in the layout is shown in Figure 11.The gate driver crosstalk suppression capability simulation platform is shown in Figure 12.Similar to the double pulse test, the crosstalk suppression capability simulation method used in this paper simulates the state of a SiC MOSFET in a half-bridge application by applying a certain intensity of dv/dt at its drain terminal and observing its gate-source voltage change when the device maintains the offstate.The model of SiC MOSFET uses Wolfspeed's product C3M0075120D, whose device parameters are shown in Table 1 It is clear that the gate driver designed in this paper has higher crosstalk suppression capability by using a multi-level drive and active Miller clamp technique.It is worth noting that although the sink current of the gate driver designed in the paper is smaller than that of CGD1200HB2P-BM3, the drop time is smaller than that of CGD1200HB2P-BM3, which is due to the operation of the Miller clamp module accelerating the turn-off process of the SiC MOSFET.

Conclusion
SiC MOSFETs have been gradually replacing traditional Si-based power devices in some applications due to their excellent material characteristics, including large forbidden bandwidth, high breakdown field strength, and good heat dissipation, which can better operate under high frequency and high-power density conditions.The faster-switching speed and higher switching frequency cause serious crosstalk problems in SiC MOSFET applications.The cause of the crosstalk problem is analyzed in this paper, and a high crosstalk suppression SiC MOSFET gate driver is proposed.Multi-level driving is used by introducing an auxiliary circuit to control the source potential of the device.The auxiliary circuit has a simple structure, simple control logic, no need to provide negative voltage externally, and adjustable negative output voltage.Active Miller clamp technology is used to further improve the crosstalk suppression capability of the gate driver.The proposed SiC MOSFET gate driver was designed based on the 0.8 μm BCD high-voltage process platform of CSMC, and the simulation verification model is based on Wolfspeed's SiC MOSFET product C3M0075120D.The designed SiC MOSFET gate driver area is 2967 μm×3180 μm.The post-layout simulation results show that the designed SiC MOSFET driver circuit can keep the positive crosstalk voltage below the threshold voltage of the device, and control the negative crosstalk voltage within the tolerable range of the device under the drain voltage change rate of 150 V/ns.The results demonstrate that compared with the conventional SiC MOSFET driver circuit, the proposed gated driver can drive the SiC MOSFET power device more reliably.

Figure 1 .
Figure1(a) shows the equivalent circuit during Q H turns on when Q L is in an off state.During Q H turns on, Q L exhibits a change in its drain-source voltage from zero up to V DS .The Miller current is generated due to rapid changes in the drain voltage of Q L , which flows to the ground through the gatedrain parasitic capacitor C GD_L and SiC MOSFET gate resistor, resulting in a positive crosstalk voltage at the low side power transistor gate.The equivalent circuit when Q H is turned off and Q L in an off state is shown in Figure1(b).Before Q H is turned off, the voltage between the drain and the source of QL is close to V DS .After Q H is turned off, the Q L drain-source voltage drops to zero, and the low-side power

Figure 2 .
Figure 2. The low-side power transistor's gate-source voltage with negative turn-off voltage

Figure 3 .
Low-side power transistor equivalent circuit (a) Time-domain equivalent circuit (b) S-domain equivalent circuit

Figure 4 . 8 VFigure 5
Figure 4. Double pulse test circuit schematicTable 1 Device parameters of C3M0075120D Parameter V a l u e Gate input capacitance ( ) 1390 pF Output Capacitance ( ) 58 pF The threshold voltage ( )2.5 V A maximum negative voltage of gate-source ( ) -8 V Figure5(a) shows the effect of different external gate resistors on the positive crosstalk voltage for the zero-voltage turn-off case.The positive crosstalk voltage is positively correlated with the gate resistance.When the external gate resistance is 2 Ω, the crosstalk voltage will cause the SiC MOSFET to turn on incorrectly.The effect of the external gate resistance on the negative crosstalk voltage is shown in Figure5(b).The larger the gate resistance is, the larger the absolute value of the negative voltage is.Figure6shows the effect of different external gate resistances on crosstalk voltages for the negative-voltage turn-off case.The crosstalk voltage shifts down overall compared to zero voltage turnoff.Under the same operating conditions, negative voltage turn-off can improve the crosstalk suppression capability of the SiC MOSFET.It should be noted, however, that when negative voltage turn-off is used, the negative spike will intensify the negative gate-source voltage, which can result in negative voltage breakdown of the SiC MOSFET.

Figure 5 .
The effect of external gate resistor on crosstalk voltage ( =0 V) (a) positive crosstalk voltage (b) negative crosstalk voltage (a) (b) Figure 6.The effect of external gate resistor on crosstalk voltage ( =-4 V) (a) positive crosstalk voltage (b) negative crosstalk voltage (a) (b) Figure 7. Crosstalk voltage variations in relation to changes in gate-source capacitance (a) positive crosstalk voltage (b) negative crosstalk voltage

Figure 9 . 2 )
Figure 9.The control timing of switch S1 1) Interval 1 [t1 -t2]: Negative crosstalk voltage suppression.When the negative voltage spike arrives, S1 keeps the on-state.Considering that the on-resistance of switch S1 is much smaller than Rp, and V gs =V C1 , V gs ≈0 V.

Figure 10 .Figure 11 .
Figure 10.The layout of the designed gate driver