ADC Clock Jitter Measurement Based on Simple Coherent Sampling Algorithm

In a high-speed sampling system, the clock jitter of analog-to-digital converters (ADCs) will greatly affect its sampling accuracy, leading to the reduction of the signal-to-noise ratio (SNR) of the system output. Therefore, it is necessary to compensate the sampling results to reduce the sampling error caused by clock jitter by measuring the distribution sequence of jitter. In this paper, the influence of clock jitter on the ADC sampling process is analyzed, and an ADC clock jitter measurement scheme based on a simple coherent sampling algorithm is investigated. This scheme can accurately measure the distribution sequence of clock jitter, and has the characteristics of low computational complexity and high precision. The simulation results show that this algorithm can accurately measure the clock jitter sequence with root-mean-square (RMS) greater than 5ps when the amplitude noise of the input signal is greater than 35dB, and the relative error is less than 5%.