Phase-locked subdivision method of digital signal based on FPGA

In order to improve the accuracy and real-time performance of the subdivision signal expression result of the photoelectric encoder in the signal dynamic measurement process, a phase-locked subdivision method of digital signal based on FPGA is proposed. The open-loop structure is used to realize the large-range detection of the grating measurement system, and the fractional frequency division method is used to realize the subdivision function of the grating moiré signal. In order to verify the effectiveness of the design, we compare the analog signal subdivision with the traditional digital phase-locked subdivision method. The experimental results show that the digital phase-locked subdivision algorithm designed in this paper can be used in the high-frequency moiré signal frequency and rate of change. The subdivision function is realized under the following conditions, which can be better applied to dynamic measurement occasions.


Introdution
Moiré grating is an important component of grating sensors in grating rulers and photoelectric encoders. It is widely used in precision measurement fields such as optical engineering precision measurement, aerospace, military measurement, etc [1-] [2] [3],used to achieve linear displacement measurement and circular Accurate measurement of arc angular displacement.
At present, there are three subdivision methods for moiré grating signals: mechanical subdivision methods, optical subdivision methods and electronic subdivision methods. Among them, the electronic subdivision method has the advantages of high subdivision accuracy and high system integration, and is widely used in the field of detection.
At present, many scholars have done a lot of work on the research of grating moiré signal subdivision. In 2008, the American Astronomical Observatory proposed an adaptive period error compensation method for Heidehain photoelectric encoder [4], which realizes the compensation of various errors of the grating signal. The disadvantage of this method is that it requires a large number of high-order matrices. Calculation, causing the system to run slowly; Sun proposed a triangular signal integral compensation method for Moiré delta interpolation error [5], in the process of experimental testing, the error compensation system reduces the interpolation error to ⅓ of the original error; Chen Ran from Changchun University of Science and Technology and others proposed a subdivision error  [6]. From the perspective of compensation effect, this error compensation method reduces the original error from 20" to less than 2"; By determining the subdivision multiplication of the input signal, a corresponding look-up table is established in the FPGA. The voltage-controlled oscillator finds the division factor based on the geology and outputs the multiplication correction. Signal, the experiment proves that this method can achieve 200 times subdivision. However, when the frequency range of the input signal is relatively high, the required look-up table occupies high logic resources of the FPGA, and the logic operation is difficult [7].
In view of the above-mentioned scholars` shortcomings in the study of subdivision errors, this paper proposes an improved digital phase-locked subdivision method for digital subdivision of moiré grating dynamic signals, by completing the circuit development of the digital subdivision algorithm on the FPGA platform. The experimental results show that the improved digital phase-locked frequency multiplication and subdivision method can effectively realize the moiré grating signal subdivision function in the dynamic measurement process. The Moiré grating measurement system is mainly composed of light source, optical system, indicating grating, grating code disc and photoelectric receiver as shown in the figure. We define the grating moiré signal :

Principle of grating moiré signal
Among them: m U is the amplitude of the input signal; θ is the phase value of the grating moiré signal, and W x / 2π θ = is the grating distance W from the θ , and x is the grating displacement.

Principle of digital phase-locked subdivision
The principle of digital phase-locked subdivision mainly includes a phase detector, a loop filter, a numerically controlled pressure cavity oscillator, and a frequency divider.
when the frequency of the input signal ) (n x is i f , the signal frequency o f of the system output signal ) (n y can be expressed as: Among them, N is the subdivision frequency.
The phase difference between the phase detector detection signal ) (n x and the frequency divider The output signal ) ( ' n p of the loop filter is the output signal of the numerically controlled oscillator, and its size will affect the frequency o f of the output signal ) (n y of the numerically controlled oscillator: From the analysis of system functions, although the photoelectric closed-loop structure can achieve better subdivision effects when the input signal is relatively stable, the loop lock requires more complicated calculations, longer execution time, and bandwidth setting of the loop filter. It will affect the frequency bandwidth of the input signal to a certain extent. Therefore, it is difficult for the traditional digital phase-locked frequency multiplication and subdivision method to output the grating moiré signal to a larger range of the moiré grating measurement system, and it has a higher impact on the precision of the phase-locked subdivision in the high-frequency domain.

Algorithm of improved phase-locked subdivision
In response to the problems raised in the previous article, the open-loop structure is used to achieve the improvement of the digital phase-locked frequency multiplication and subdivision method. The principle structure is shown in the figure: Realize the equivalent effect of fractional frequency division under different input signals.

FPGA implementation of phase-locked subdivision method
In order to ensure the real-time and rapidity of the digital subdivision circuit. The overall circuit block diagram of the moiré signal subdivision processing based on the improved digital phase-locked subdivision method is shown in Fig.3. The digital subdivision system is mainly divided into two parts, the preprocessing circuit and the FPGA processing module. Among them, the preprocessing module includes two parts: digital signal sampling and analog-to-digital conversion, which are used to collect and amplify the output signal of the moiré grating; in the FPGA processing module, the quantization parameter solving module uses the edge detection and counting device to The input signal is processed to obtain the quantized value ) ( ' n y . In order to effectively improve the dynamic detection capability of the detection system, the quantization parameter solving module uses the parallel structure of FPGA to solve the In order to reduce the system delay problem in the process of parameter solving, while comparing 1 k and 2 k , the 2 N value can be obtained by shifting. Then through the comparator, compare the size relationship between and 2 N , so as to determine the value of the number of output groups.  , and the output delay only needs 10ns. It can be seen that the optimized digital phase-locked frequency multiplication has the characteristics of high frequency adaptability, high calculation efficiency, and high signal output accuracy.In terms of hardware resource occupancy,the optimized logic algorithm occupies less resources and performs more efficiently.

Conclusion
This paper proposes an optimized digital phase-locked subdivision method, and analyzes the effect of the decimal frequency division algorithm on system error reduction. A digital phase-locked subdivision circuit based on FPGA is proposed to optimize the circuit design of the flip-book solving module. The experimental results can show that the improved digital phase-locked frequency multiplication and subdivision method can subdivide the moiré grating signals in different frequency states. Compared with the traditional digital phase-locked frequency multiplication and subdivision method, the improved digital lock The phase doubling frequency subdivision method has a significant improvement in accuracy and computational efficiency in terms of realizing the signal subdivision function.