Realization and optimization of a new spike detection algorithm logic circuit

At present, artificial intelligence has increasingly become the most promising and essential major. The interdisciplinary cooperation between the integrated circuit and artificial intelligence brings infinite possibilities. In the convolutional neural network area, in order to achieve the valuable output, the comparison between values is often encountered. The output is obtained by comparison between the result after the convolution calculation with the designed threshold. Therefore, our team not only design a 4-bit binary comparator hardware logic circuit to complete the task but also discuss and verify the feasibility and performance characteristics of the program from the perspective of energy and time delay. As for the overall framework, we design a convenient circuit that converts the complement code into the original code and chooses a CLA adder to accomplish this part. Using this kind of adder can ideally help us reduce the time delay at the expense of a complicated circuit schematic. In the comparator part, we design a high-quality circuit framework. The strategy of our circuit is to compare the relationship between the four-bit binary code and the threshold bit by bit from MSB to LSB, which performs better than the original 4-bit comparator, and we design two outputs that can legibly illustrate the relationship between two values. We use logic effort to discuss the normalized delay in our project. Besides, we find the connection between the energy and the delay by calculation. Finally, we design a trade-off function to make the optimization of energy and delay together with respect to voltage.