A Demodulation Circuit For Analog Front End Of Passive Tag Chip

The demodulation circuit designed in this paper is suitable for the analog front end of passive UHF RFID tag chip, which can handle ASK signals with large changes in amplitude, modulation depth and signal frequency. Its performance meets the requirements of standards ISO/IEC 18000-6C and GB/T 29768-2013. Envelope detection circuit and limiter circuit are simple in structure and do not consume power. The comparison reference voltage is taken according to the average value of the envelope high and low levels, and is less affected by the dynamic changes of the input signal. Changing the width-to-length ratio of the MOSFETs in the feedback path of the comparator can adjust the hysteresis, with strong noise suppression and controllable sensitivity. The demodulator is implemented with TSMC 0.18 μm standard CMOS process. The simulation results show that the ASK signal modulation depth that the demodulator can handle is as low as 30%, and the maximum pulse width demodulation error is only 0.43%.


Introduction
Radio frequency identification (RFID) technology relies on radio waves to realize non-contact data exchange and target identification between reader and tag chip. The ultra-high frequency (UHF, 300 MHz ~ 3 GHz) radio frequency system has the characteristics of long identification distance, fast transmission speed and small antenna size [1]. The current international mainstream standards and national standards for UHF RFID systems are ISO/IEC 18000-6C and GB/T 29768-2013, respectively. It can be known from the two standards that the system forward link signal is a wave modulated by amplitude keying (ASK) with a modulation depth of 30% to 100%, and the baseband signal frequency is 40 kHz to 160 kHz.
The structure of the tag chip demodulator is generally a low-pass filter followed by a comparator. Its comparison reference voltage takes half of the envelope peak voltage. This circuit has a simple structure but cannot demodulate ASK signals with a modulation depth of less than 50%. Some schemes are voltage-compensated envelope detector followed by peak detection circuit. Although this type of circuit improves the demodulation sensitivity, the structure of the detection circuit is complex and requires a working power supply [2]. This paper designs a UHF RFID demodulator with no power consumption for the first two sub-circuits and based on average detection. It can handle RF signals with large changes in amplitude, modulation depth and signal frequency. The circuit performance meets the requirements of ISO/IEC 18000-6C and GB/T 29768-2013.

Design of UHF RFID Signal Demodulator
The structure of the UHF RFID signal demodulator designed in this paper is shown in Figure 1. Demodulator of UHF RFID signal The received radio frequency signal modulated by amplitude keying (ASK) is transmitted to the envelope detector to extract the envelope of the modulated signal. The limiter circuit can avoid circuit abnormalities caused by large envelope signals. The limiting voltage is divided into two lines: one is connected to the comparator; the other is transmitted to the reference voltage generator to generate the comparison reference value . The comparator compares and to determine the high or low level, and finally outputs the digital signal .

Envelope Detector
As shown in Figure 2, a better scheme to extract ASK signal envelope is voltage multiplier plus lowpass filter [3]. The circuit structure is very simple, does not require additional power supply, does not consume power, and is suitable for use in passive tag chips.  Figure 2 form a one-stage voltage doubler rectifier circuit. When the value of is less than the threshold voltage of the MOSFET, that is, − < < , both M1 and M2 are cut off. When is in the negative half cycle and < − , M2 is turned on, and the current flows from Ground through M2 to charge C1. Assuming that the peak value of is , the voltage on C1 will be 1 = −( − ) at this time. As the input voltage rises, M2 will be cut off, and according to the conservation of charge, the voltage on C1 will remain unchanged. When > , M1 turns on and starts charging C2. When reaches the peak value of the positive half cycle, the ideal voltage value of C2 should be: When gradually drops from the peak value of the positive half cycle to < , M1 is cut off and C2 discharges through R1. Since the charging time constant 1 = 1 • 2 is much smaller than the discharge time constant 2 = 1 • 2, 2 is better maintained near the peak value of the positive half cycle of . 2 is . The simulation result of the envelope detection circuit given in the second row of Figure 6 shows: the passive and power-free voltage doubler rectifier and low-pass filter structure successfully extract the envelope of the radio frequency signal.

Limiter
When the distance to the reader is closer, the energy received by the tag is larger. The limiter circuit can avoid the abnormality of the subsequent circuit caused by the large envelope signal. As shown in Figure  3, the entire limiter circuit is not connected to a working power source and has no energy consumption.  Figure 3.

Limiter circuit
When is low, the gate-source voltage 5 of M5 is less than its threshold voltage 5 , so 6 must be less than 6 . At this time, M5 and M6 are both in the cut-off state and the output voltage is equal to the input voltage .When 5 > 5 and 6 < 6 , M5 is on and M6 is off. The resistance R1 and the equivalent resistance 5 of M5 divide the input voltage. At this time, the output voltage is: When rises continuously so that 6 > 6 , both M5 and M6 are turned on. The output voltage is: (3) Figure 4 shows the simulation results of the limiter circuit. When the input voltage is 0~1.5 V, the output voltage is approximately equal to the input voltage. When the input voltage is 1.5~8 V, the output voltage is limited to 1.8 V.

Figure 4.
Simulation results of limiter

Reference Voltage Generator
Divide into two lines: one is connected to the comparator; the other is connected to the reference voltage generator to generate the average voltage . If you want to demodulate radio frequency signals with different amplitudes and different modulation depths, the reference voltage used for comparison should be dynamically determined according to the high and low levels of . The reference voltage generator based on peak value and valley value detection satisfies this requirement well. Its circuit structure is shown as in Figure 5 [5]. The operational amplifier in the circuit can adopt a general operational amplifier structure.
At the initial moment, the voltages on capacitors C1, C2 and C3 are all zero. When the input terminal is high level, the voltage of the inverting terminal of OPA1 and OPA2 is greater than their in-phase terminal. Therefore, both operational amplifiers output low level. M1  The simulation result of the reference voltage generator is shown in the third row of Figure 6: The actual (dashed line) generated is successfully placed between the high and low levels of .

Figure 6.
Simulation result of reference voltage generator

Hysteresis Comparator
Ripple voltage input to an ordinary single-threshold comparator will produce back and forth jitter at the output. The hysteresis comparator has the ability to suppress noise whose amplitude is within the range of hysteresis ∆ . The structure of the hysteresis comparator designed in Figure 7 is a two-stage amplifier followed by a two-stage inverter [6]. The differential input MOSFETs M1 and M2 have the same specifications. Now assume that is grounded. When the input voltage is far less than 0, the relationship between the gate-source voltage of M1 and M2 is: | 1 | ≪ | 2 |. Then M2 turns on and M1 turns off. The turned-on M2 causes M7 and M8 to turn on, but M1 cutoff makes M5 and M6 cut off and makes M7 in the deep linear region. So there is 9 = 2 = 8 (I 2 , I 8 , and I 9 are the drain-source currents of MOSFETS M2, M8, and M9, respectively.). At this time, M3 is off and M4 is on, and the comparator outputs a low level.
The input voltage gradually increases from low to high, causing | 2 | to continue to decrease. Then M1 gradually leaves the cut-off state. The ultimate role of M7-M8 mirroring is to: (W/L) 7 and (W/L) 8 in formula (5) are the conductive channel width-to-length ratios of MOSFET M7 and M8, respectively. When the rising makes M1 gradually turn on and makes 1 increase to the mirror value 7 , the output of the comparator switches from low to high. Therefore, When 1 = 7 , the From 1 = 7 , 2 = 8 , 9 = 1 + 2 and equation (5), the following equation can be derived: From equations (6) to (8) and the current formula of the saturation region of the P-MOSFET (where is the surface electron mobility of the P-MOSFET, is the gate capacitance per unit area): Similarly, the lower threshold voltage can be derived as: The bias current 9 of the circuit is provided by the current mirror M9. If the aspect ratio of M1 (M2) has been determined, the upper and lower threshold voltages and hysteresis can be determined by changing the aspect ratios of M5, M6, M7 and M8. Figure 8 shows the simulation result of the hysteresis response of the comparator: the designed hysteresis of this circuit ∆ is 20 mV.

Figure 8.
Hysteresis response of comparator

Circuit Layout
In order to reduce the mutual interference between circuit devices, each sub-circuit and each amplifier are arranged as independent module units. There are two guard rings around each unit: the inside is the P guard ring connected to the ground, and the outside is the N guard ring connected to the power supply. The combination of inner P and outer N forms a PN junction wall around the outside of the module to protect the inside of the module from external noise. The capacitors, resistors, P-MOSFETs and N-MOSFETs in each module unit should be arranged separately. A P guard ring connected to the ground is arranged around each capacitance area, resistance area and N-MOSFET area. This protects the holes in the P substrate in the ring from being injected by electrons outside the ring. In addition, the P-ring of the N-MOSFET area can also be used as the substrate of the MOSFET. An N-ring connected to the power supply is arranged around the P-MOSFET area: This not only protects the electrons in the Nwell in the ring from being absorbed by the holes outside the ring, but also serves as the substrate of the P-MOSFET.
The current mirror controls the current of each branch by changing the width-to-length ratio of each MOSFET. In order to obtain an accurate proportional current, the MOSFET in the current mirror should adopt interdigital structure. Such as hysteresis comparator M5-M6, M7-M8, M9-M10 and M11-M12. Each MOSFET that needs to be matched should have the same channel length. The matching of the two MOSFETs uses the ABBA symmetrical interdigital structure and the three uses ABCCBA.
Because the MOSFET on the differential input terminal is extremely sensitive to signals, the accuracy of the one-dimensional interdigital structure is insufficient. The two-dimensional co-centroid array has better consistency, symmetry, dispersion, compactness and directionality. M1-M2 and M3-M4 in the hysteresis comparator are differential input pairs. The channel lengths of these MOSFETs that need to be matched should be the same. The two-dimensional high-precision matching MOSFET's fingers should be divided into two rows: the layout of the first row is ABBA and the second row is BAAB to form an ABBA BAAB cross-coupled pair. Figure 9 shows the demodulation circuit layout of the tape-out.

OPA1
OPA2 Reference Voltage Generator Envelope Detector Limiter Comparator Figure 9. Layout of demodulation circuit

System Simulation of Demodulator
The pre-simulation and post-simulation of the whole circuit use cadence spectre. The working power supply of the circuit is 1.8 V during simulation. The carrier of the radio frequency signal is a sine wave of 915 MHz. The simulation conclusion is obtained by observing and measuring the output signal and calculating the maximum deviation. Figure 10 shows the simulation results of ASK signals with three different amplitudes, modulation depths and pulse frequencies. The widths of the three input pulse signals are 3.125us, 6.25us and 12.5us respectively. The actual measured output pulse width is 3.116us, 6.277us and 12.499us respectively. Thus, The pulse width errors are -0.29%, 0.43% and -0.01%, respectively. Protocols ISO/IEC 18000-6C and GB/T 29768-2013 use PIE and TPP to encode baseband data respectively. Both of these codes can be converted into non-return-to-zero (NRZ). Now arbitrarily give three groups of 8-bit NRZ baseband data, and use different depths to modulate the carrier to generate ASK signals. Use them as incentives for the circuit. The output response is shown in Figure 11: The baseband signal is accurately and completely demodulated by this circuit. The demodulation circuit designed in this paper with good dynamic performance and extremely low demodulation error has been applied to an ultra-low power label chip that has been taped out. The position of the demodulation module in the chip is shown in the photomicrograph in Figure 12. Micrograph of the chip

Conclusion
The envelope detection circuit and limiter circuit in this paper do not need power supply and consume no power, so they are suitable for passive tags. The reference voltage generator can generate the corresponding average value reference voltage according to the high and low level of the signal envelope, so its dynamic adaptation performance is better. Finally, after the judgment of a hysteresis comparator with strong noise suppression, it can demodulate ASK radio frequency signals with various amplitudes, various modulation depths and various code rates. Reasonable layout technology minimizes device mismatch and parasitic effects, so the circuit has a good front-end consistency. The circuit is implemented using TSMC 0.18 μm standard CMOS process. The simulation results of ASK signal combinations of various amplitudes, modulation depths and pulse frequencies show that the maximum error of the signal pulse width is only 0.43%. The demodulator can accurately and completely process the PIE and TPP encoding of the protocol ISO/IEC 18000-6C and GB/T 29768-2013. This circuit has been used as a demodulation module in passive tag chips and successfully taped out.