Analytical Modeling of Triple-Material Trigate Junctionless Tunnel Field Effect Transistor

An analytical two-dimensional (2D) model is developed to obtain expressions for various parameters of triple-material trigate junctionless tunnel field-effect transistors (TMTG-JTFETs). The 2D Poisson’s equation uses the superposition approximation method to calculate the sum of potentials arising from different point charges. The electric field distribution in the channel is obtained from the gradient of the electric potential. The drain current of the device is calculated using the Kane’s model in the presence of an electric field and a band structure. The TMTG-JTFET, with a channel length of 40nm, exhibits significant electrical characteristics with very low off-current (Ioff) and high on-current compared to a dual-material double-gate TFET. To validate the model, analytical results are confirmed via comparison with technology computer-aided design simulation results.


Introduction
Short-channel effects have pronounced implications for the scaling of conventional-bulk-planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and drive us to investigate multigate structures and other novel devices (junctionless devices, tunneling devices, etc.).Scaling down MOSFETs to nanometer dimensions exponentially increases the leakage current (I off ) via the scaling of the threshold voltage and oxide thickness. Reducing the subthreshold swing is necessary to reduce the power without excessively increasing the leakage current. Because of the nonscalability of the threshold voltage in MOSFETs, the subthreshold slope cannot be reduced below 60mV/dec. the subthreshold slope, a band-to-band tunneling (BTBT) current mechanism is used rather than a thermionic current mechanism in MOSFETs [1][2][3]. Tunnel FETs (TFETs) are expected to operate at voltages as low as 300mV and achieve a subthreshold swing of<60mV/decvia the BTBT mechanism [4]. TFETs are the most promising device for ultralow-power applications because they are steepslope devices that give the lowest I off and largest I on /I off at a reduced V DD . Because TFET structures suffer from lower I on compared to MOSFET structures owing to the tunneling current transport phenomenon, various structures have been investigated to improve the I on /I off ratio-e.g., single gates [5], double gates [6], dual-material double gates [7],gate all around FETs [8],vertical gates [9], heterojunctions [10], stacked gate oxides [11], and junctionless TFETs (JTFETs) [12]. The TFET oncurrent can also be boosted by employing bandgap engineering [13], doping engineering [14], geometry engineering [15], and gate work function engineering [16]. An analytical TFET model is essential to provide insight into the working of the steep subthreshold switch and its switching behavior for low-power circuits. Several two-dimensional (2D) analytical models for different TFET structures have been investigated to solve Poisson's equation using the parabolic approximation [17][18][19][20] and the superposition approximation [21,22] to compute the surface potential, electric field, and tunneling rate generation of TFETs. The superposition approximation has been used by Lee et al. [21] and Gholizadeh et al. [22] to develop a 2D analytical model that predicts the impacts of structural parameters and includes the influences of the mobile charges on the potential profile and the drain bias on the current. In this paper, we have modeled the triple-material trigate JTFET (TMTG-JTFET) and derived an analytical expression for the drain current using the superposition approximation method. When the analytical results are compared with technology computer-aided design (TCAD) results [23], the device model using the superposition approximation is shown to be more effective than the parabolic approximation.

Model derivation
The structure of a TMTG-JTFET is shown in Fig.1. The channel length (L) is 40nm, and the uniform channel doping n i = 810 18 cm −3 . The thicknesses of the gate dielectric (T i ) and the junction depth (T si ) are considered to be 3 and 8 nm, respectively. The junctionless transistors are turned on by varying the middle gate voltage from 0 to 1 V and by fixing V G1 as positive and V G2 as negative, tunneling occurs in the source-channel junction [23]. The workfunctions for gate 1, gate 2, and the middle gate are considered to be 4.26, 4.6, and 4.28eV, respectively. The gate voltage determines the transistor operation, and Vadivukkarasi et al. [24] investigated the optimal combination of gate 1 voltage V G1 and gate 2 voltage V G2 .  (1) where ε si is the permittivity of the silicon, q is the electronic charge, V t = 0.025V is the energy gained by the electrons to jump to the conduction band energy level, and V indicates the population of electrons in the energy band resulting from the voltage applied at the source and drain. The  (1), and its solution is obtained using the superposition approximation method [25]: where v(y) and ψ(x,y) are the solutions of the one-dimensional (1D) Poisson's equation in (3.1) and the 2D Laplace equation in (3.6), respectively. As per Pao-Sah's gradual channel approximation [26], the potential in the intrinsic region is given as The solution to the 1D Poisson's equation is obtained by integrating (3) twice as described by Taur etal. [5]: The potential is constant along the channel, and this is validated from the TCAD simulator. For a given value of V GS = 1 V and V = 2 V, β, an electrostatic temperature coefficient, can be solved using the Newton-Raphson method from (5) After simplifying (5), we obtain β = 1.5, where V t and q are the thermal voltage and electron charge, respectively; the permittivity of silicon is ε si = 11.68 F/m; the permittivity of the insulator is ε i =3.9 F/m; the thickness of the silicon is T si = 8 nm; the thickness of the insulator is T i = 3 nm; the intrinsic carrier density is n i =810 18 cm −3 ; ∆ϕ = 0.026eV is the work function difference between ϕ M (metal) and ϕ S (semiconductor) used to control the behaviour of the JTFET; and the potential V is equal to the drain-to-source voltage V DS , varies at the source-channel junction, and remains constant in the channel.
The 2D Laplace equation is given as (6) and its solution is (7) where the eigenfunctions and can be written as ∑ and ∑ where the first-order coefficients and can be evaluated from [27] and capture the electrostatic potential in the channel region [28]:  (9) λ n is the scale length of the JTFET structure, which is mathematically defined as (10) Upon solving (10), for a trigate n = 3, the eigenvalues λ 1 = 2.59610 −8 , λ 2 =1.29810 −8 , λ 3 = 0.86410 −8 are obtained from (11.a) (11.b) (11.c) where T i andT si are the thicknesses of the insulator and silicon, respectively. The eigenvalues λ 1 , λ 2 and λ 3 are used in the calculation of first-order coefficients b n and c n .
Upon solving for the basic characteristics of Bessel and Neuman functions [27], the values of firstorder coefficients b n and c n are found to be (12) and From (12) and (13), the first-order coefficients b 1 = 0.156, b 2 = 0.207, b 3 = 0.375, c 1 = 2.239, c 2 = 2.232, and c 3 = 3.578 are obtained for the trigate by substituting n = 3, where ∆ϕ 1 = 0.6eV, ∆ϕ 2 = 0.28eV, and ∆ϕ 3 = 0.26eV represent the work function differences among the three regions, respectively; V GS is the gate-to-source voltage; V DS is the drain-to-source voltage; E G is the bandgap energy in electron volts; and q is the magnitude of electronic charge in coulombs.
The first-order eigenfunction is used to calculate the potential in the channel and is expressed as (14) Substituting the values of the 1D Poisson's equation into the above equation, we obtain ψ(x,y) = 2.86V for a mesh point in the middle of the channel.
The lateral electric field E y (x,y) resulting from the applied gate bias voltage is calculated as the derivative of the potential per unit length from (14) and is (15) From (15), the maximal value of E y (x,y) can be obtained at the middle of the channel .In contrast to the results of [29] and [30], the field is maximized along the source-channel junction and decreases to a minimal value along the channel. To obtain accurate results, we can consider higher-order terms to capture a sharper potential in the tunneling region. A Taylor series expansion is used to calculate the electric field and is written as (16) From (16), the electric field E y (x,y) of the TMTG-JTFET can be obtained as 0.12810 6 V/cm by taking the root mean square of vector components E y1 , E y2 ,andE y3 .

Drain current derivation
The drain current expression for the JTFET is derived from Kane's model [31] using a dynamic nonlocal tunneling model based on the band structure and electric field. The drain current along the channel is expressed as (17) where A and B are the process-dependent parameters of Kane's model (because Kane's model has been used in an analytical model, the same values of A = 0.1810 −16 V/cm and B = −3.8810 −16 V/cm have been included in the simulation), D = 2.5 for an indirect tunneling process, and the average electric field can be calculated as  where l path = 40 nm is the tunneling path length and E g = 1.1eV is the bandgap energy. By substituting the electric field from (16) into (17), the drain current is obtained as 1.6810 −−8 A/µm.

Results and discussion
In this section, the analytical results for a TMTG-JTFET with three gates are compared with the device simulator results from Sentaurus TCAD. The device parameters for the simulated structure are given in Table I. The middle gate acts as a controlling gate V G ; its voltage is varied from 0 to 2 V to turn the device on. The gate 2 voltage (V G2 ) near the source and the gate 1 voltage (V G1 ) near the drain region convert the junctionless device into a P-i-N structure. Because the operation of the device is based on the gate voltage, side gate voltages are fixed to establish the band structure of the device. Fig.2 illustrates the effect of variation of I ON on V G1 for different values ofV G2. It is evident that the maximal value ofV G1 is chosen in the range of 0.7 to 1.3 V if I ON is constrained. The energy band diagram of the JTFET with V G2 =−0.7V for V G1 =0.7 and 1.3Vis illustrated in Fig.3,which shows the BTBT rate as V G1 increases.  Fig. 3. Energy band diagram with V G2 as−0.7 V for different values of V G1 Fig. 4shows the effect of varying I ON on V G2 for different values of V G1 .It can be observed that I ON increases when V G2 becomes more negative. The energy band diagram, with V G2 =−0.7V forV G1 =−0.7 and 0.7V is illustrated in Fig.5, which shows that the BTBT rate increases asV G2 becomes more negative.  (14), which increases the electric field in the tunneling region.   Fig. 7, the first-order eigenfunction works well to describe the channel potential, and higher-order approximations of the Taylor series expansion are used to capture the potential in the source-channel junction. In the middle of the channel, the electrostatic potential ψ(x,y)is constant and is obtained as 2.86V from(14)by using the superposition approximation method, and the analytical result is validated with the results of the TCAD device simulator. To model the electric field distribution along the channel, we have considered only the lateral electric field, because the tunneling path follows the channel direction. It is evident from Fig.8that the highest electric field is obtained in the source-channel junction and drops to its minimal value in the middle of the channel owing to constant potential, as shown in Fig.7. A maximal electric field of 0.12810 6 V/cm has been derived by using the superposition approximation method with (16), and the analytical result is compared with the simulator result.  Fig. 8. TMTG-JTFET electric field along the channel The drain current behavior for the JTFET device is shown in Fig.9. The proposed analytical model Fig. 9. I D -V GS characteristics of TMTG-JTFET for various gate voltages offers an on-current of 1.6810 −8 or V G = 1 V at fixed side voltages of V G1 = 0.7V and V G2 = −1.1 V. It is evident from Fig.9 that the drain current increases with increasing gate voltage, owing to the presence of a high-k material for the gate (Si 3 N 4 , k = 7.5) and low-k spacers (SiO 2 , k = 3.9). A low off-current of 10 −12 also be applied to other materials such as III-V compound semiconductors. A higher drain current and a steeper subthreshold slope can be obtained by reducing the thickness of silicon, using high-k dielectrics such as HfO 2 , ZrO 2 , and TiO 2 as gate material and by work function engineering.

Conclusion
In this paper, the electrostatic potential of a TMTG-JTFET has been developed from the 2D Poisson's equation using the superposition approximation method; its derivative gives the electric field. The drain current is obtained by integrating the BTBT generation rate over the channel thickness. Maximal I ON is achieved by giving a positive voltage to the drain and a negative voltage to 10 the source. The JTFET device with three gates offers an I ON of 1.6810 −8 A/μm at V G =1 V, V G1 = 0.7 V, and V G2 =−1.1 V. Analytical results for the electrostatic potential, electric field, and drain current obtained using the superposition approximation method are in good agreement with the TCAD results.