Evaluation of flux trapping moat position on AQFP cell performance

With recent advances in InductEx and the TetraHenry numerical engine, it is now possible to analyze the coupling of trapped flux in moats to superconductor circuit structures. Here we show the analysis of moat position in the layout of an adiabatic quantum-flux-parametron (AQFP) buffer cell on the coupling to critical inductors such as the load inductor. This inductor is often carefully laid out to balance current flow and cancel out stray coupling between clock and dc current excitation lines. We investigate the effect of trapped flux that couples asymmetrically to the circuit—either due to the moat position and shape or due to only one of a symmetrical duo of moats being filled with a trapped fluxon—on circuit operating margin and performance. We conclude with suggestions on moat placement to reduce the chances of circuit failure when fluxons are trapped in the moats.


Introduction
Flux trapping in type-II superconductor thin films, such as the ground planes of niobium-based integrated circuits, has long been known to degrade circuit operating margins [1]. Moats are used as low energy flux trapping locations [2] to lower the probality of Pearl vortex formation [3] in critical circuit structures such as Josephson junctions.
SQUID microscope imaging of fluxons trapped in thin films and moats [4,5,6,7] has helped superconductor integrated circuit designers understand how fluxons are attracted to moats.
Recently, new methods were developed to analyse the coupling of fluxons in superconducting holes to superconducting structures in a circuit layout [8,9] and incorporated in InductEx [10] and TetraHenry [11]. The phase-based circuit simulator JoSIM [12] was also developed to simulate the compact simulation models of trapped fluxons in superconductor circuit simulations. The extraction tools, compact simulation models and JoSIM engine were validated through experimental investigation of SQUIDs coupled to different moat configurations [13].
With the tools validated, investigations were done on the coupling between fluxons in different moats and SQUID loop inductors [14], and it was shown that fluxons trapped in moats induce currents in superconductor circuit loops that alter Josephson junction bias points and can significantly degrade the operational margins of such circuits. In this work we investigate the effects of fluxons trapped in moats near adiabatic quantumflux-parametron (AQFP) cells on circuit operation, and draw conclusions the effectiveness of several moat configurations.

AQFP buffer simulation
For this investigation we analysed a standard AQFP buffer cell [15], for which the circuit schematic is shown in Figure 1(a). A cascaded test circuit was created for simulation, as shown in Figure 1(b), with ac clock sources, a dc bias and input signal applied. The second cell (labelled "2") is subjected to flux trapping in moats.
The AQFP buffer cell layout is taken from the cell library for the 10 kA cm −2 highspeed standard process provided by the National Institute of Advanced Industrial Science and Technology (AIST) in Japan, as presented in [16]. Several moat layout configurations were implemented, labelled from A1 to I2 as shown in Figure 2.
Circuit parameters are extracted from the layout with InductEx to account for all significant mutual inductance (the layout marked for extraction in InductEx is shown in Figure 4), and simulation was done with JoSIM [12] because it allows phase-based simulation that is a requirement for compact models that include fluxons on moats. The simulation results for the A circuit are shown in Figure 3(a) for no fluxons in any moat, and in Figure 3(b) when there are three fluxons (oriented upwards from the chip surface) in moat A2. The nominal circuit, without any fluxons in moats, acts as a buffer chain that propagates high inputs from input current I in to the output of each buffer at I Q1 to I Q4 . With three fluxons trapped in moat A2, buffer 2 fails to produce sufficient output current to drive buffer 3, so that the outputs of buffers 3 and 4 remain low.

AQFP buffer layout and InductEx model
The AQFP buffer layout for the AIST HSTP process is shown in Figure 4, labelled for inductance extraction with InductEx. Moats are included in the extraction with "F" labels in every moat.
The moats under investigation are shown in Figure 2. Due to symmetry, we only consider moats to the left of each layout. Moats A1 and A2 represent the typical configuration. Here we also investigated shorter moats B2 and B3 parallel to the output transformer and moats C2 and C3 that try to limit the asymmetry with the output transformer. Moat D2 is an attempt to lessen the asymmetry of B2, moats E2 and E3 are wider to increase moat inductance and reduce the amplitude of the circulating current due to a trapped fluxon, moat F2 is perpendicular to the  output transformer to reduce the distance that circulating current flows parallel to the output transformer, and moat G2 is an attempt to reduce the asymmetry with the output transformer. Finally, moat H2 mimics a Pearl vortex inside the output transformer coil, while I2 examines the result of a moat inside the output transformer coil.

Simulation results
Rather than examine the change in bias margins for the AQFP buffer cell as a function of the number of fluxons in each moat, we measured the current in the main branches of the AQFP buffer cell when exactly one fluxon of either positive or negative orientation is added to one moat at a time. This provides information on the sensitivity of branch currents to fluxons in the moats. The results are shown in Table 1 We also measured the number of fluxons in each moat that causes the simulation to fail. The lower the number of fluxons for circuit failure, the more sensitive the circuit is to the specific moat. Results are shown in Table 2.

Discussion on moat design and placement
We note that moats A1 to I1 protect the Josephson junctions and couple weakly to L 1 , L 2 , L q and L out .
Moats A2, B2, B3, D2 and G2 couple asymmetrically to L q and L out and induce significant currents in L q even when one fluxon is trapped in the moat.
The perpendicular moat F2 exhibits low coupling, and a fishbone structure of parallel moats is thus a good design choice, at the expense of decreased placement density for cells.
Thicker moats E2 and E3 reduce coupling to the circuit with a low area cost, and are preferable to A2 or B2 and B3.
Finally, moats C2, C3, H2 and I2 guarantee circuit failure with one trapped fluxon. From the results for these moats, we can define a fluxon exclusion zone that covers the output transformer (L q and L out ) and the gap between this transformer and L 1 and L 2 . No moats are allowed in this zone, and Pearl vortex formation must be prevented with nearby moats.

Conclusion
We investigated the effects of fluxons in moats on an AQFP buffer cell, and found that moats that couple asymmetrically to the output transformer significantly disturb circuit operation. Wider moats (covering more surface area) reduce such coupling, and where space is avialable, moats perpendicular to the sides of the transformer coil perform even better. We also showed that flux trapping inside the transformer coil will destroy circuit operation.
Finally it may be worth considering different designs for the output transformer to enable better symmetry to moats while retaining the necessary low coupling from this transformer to other inductors in the circuit.