Secure Scan Chain using Test Port for Tester Authentication

The principal goal of the paper is to reduce hacking from hackers. In order to reduce this access to the scan architecture of known vector is limited by test authentication and also limits the attempts for the application of test vector to observe the result of scan architecture. If the password is correct it move on to the next step otherwise, it again move to login window.


INTRODUCTION
Scan structure also can be applied as underhand means of access for hackers to interrupt chip protection. Test structure used to hack the hardware implementations such us Advanced Encryption Standard, Rivest Shamir Adelman encryption etc. The steady test structure to guard Circuit under test in opposition to experiment-primarily based totally assaults at the same time as keeping a excessive controllability and observability.
There are normally used strategies to offer safety for experiment structure in opposition to capacity assaults. First, the get admission to the test chain is restrained the use of public condition.
The steady test structure technique permits the test chain but during the test output phase, the information is converted. In this technique, test shape is changed the use of comparator, AND gate, shift register, LFSR (Linear Feedback Shift Register).

PROPOSED METHOD
A. Authentication Block Components for tester: The condition used for authentication through circuit under test are defined below: Condition 1: Once the relationship among the circuit under test and authentication testers is started, the circuit under test applied a Clock sign to the testers to reach the key from the testers via Dout Condition 2: The authentication testers gets the Clock sign and transfer the key to circuit under test Condition 3: The circuit under test gets the key and it similarity with a previous loaded key inside the authentication Condition 4: If the authentication is done completely, the 2 nd layer of protection is turn on. Otherwise, the circuit under test transfer an authentication is not succeed and it send that message to the tester.
Step 5: The operation failed, the demo (trail) counter is increased. If the remember reaches a already defined number, the pass or fail condition is not enabled to flip blocks and its get admission to the stable experiment. The authentication block diagram in Fig. 1 It consists of n bit register and n bit tester input both can be given as input to the exclusive or gate and its output is applied to the n bit counter. The output of the n bit counter is applied to input of flip-flop. Flip-flop stores a single bit data and it send information to access to scan chain. With the help of trail counter is sends the information to authentication key request.

B. Scan primarily based totally attacks:
Test chains are planned to offer get entry to CUT take a look at thru check get entry to port so as to practice take a look at information to CUT all through the check condition.
The test-primarily based totally assault contains 4 workings it's mentioned below: i) Test-input It is split into two levels. 1 st one is to check statistics are continuous loaded into the experiment turn-flops linked to enter input .2 nd one is to the loaded facts is carried out as a take a look at the CUT.

ii) Result Observed
Circuit under test reaction is applied to the check vector and it's covered through the test and its turn on the output connection iii) Test -output Shifting the observed result which is covered with the aid of using the experiment-turn to make the facts to be had output data has been tested

iv) Final Register
The application of test vector to observe the result of scan architecture. If the password is correct it move on to the next step otherwise, it again move to login window The input(password) is fig2 given to the shift register and corresponding output is given to 2 bit counter that is given to comparator and compare the value for corresponding output and get the output in lfsr (linear shift feedback shift register).If the input(password) is wrong, then the comparator output goes to AND gate and it moves to login window(shift register)

Fig3: modified method1
Step1: The input (password) is given to the shift register which shifts the input values, the shifted values given to the 2 bit counter The typically used linear feature of only one bits is XOR. An LFSR is a most usually a register whose enter bit is forced through the logic gates like XOR of a few bits of the general shift register value. Step2: If the password count is given as 3, it counts the value until 3,and propagate the corresponding output to the comparator Step3: The comparator compares the corresponding output of the counter and gives the output.
Step4: The comparator output is given to the LFSR, which shifts the values as output Step5: If the password is correct it immediately propagate the exact output, otherwise it will move to AND gate and it goes to initial stage.
The input(password) is given to the shift register and corresponding output is given to 2 bit counter that is given to comparator and compare the value for corresponding output and get the output in lfsr (linear shift feedback shift register).If the input(password) is wrong, then the comparator output goes to AND gate and it moves to login window(shift register) as shown in fig7