Universal Verification Methodology Based Verification of UART Protocol

Verification today acts as a constriction of any complex VLSI design. Bringing out improved verification efficiency is a must. Most of the computers and microcontrollers contain a number of serial data ports. These data ports are used to connect with devices such as keyboards and printers which are basically serial input and output devices. Transmission and reception of serial data from an isolated location can be done with the help of a modem connected to the serial port. UART- Universal Asynchronous Receiver and transmitter is a hardware device which facilitates serial transmission and reception of data. In this work presented here, the UART has been designed with the use of the industry standard Verilog HDL code and the verification of the protocol has been done using system Verilog code in UVM environment. The UVM based verification methodology can significantly reduce the time needed for verification.


Introduction
Most UART is a computer hardware device that is used for serial communication. The device is used for data exchange between a computer and outer devices as it provides high reliability and capability of data transmitting to a long distance. It is used to control the process of converting parallel data into serial data. It consists of one transmitter and one receiver.
The basic structure of the UART illustrating the process of both transmission and reception is shown in Figure1.

Figure 1 Illustration of transmission and reception of UART
The conventional verification techniques do not provide verification environments which can be reused over again. The time to market of these conventional techniques is also very slow [1]. The Universal Verification Methodology (UVM) library contains reclaimable components as well as 2 environments for test with the help of System Verilog. The UVM is a standard methodology used for the verification of integrated circuit designs. Reusability, scalability, interoperability and all these things can be achieved through methodology only like UVM which serves as a great advantage of using UVM [2].
The Section 2 in this paper presents a discussion on UART protocol and it's working. Section 3 discusses about the Universal Verification Methodology and the following section i.e. section 4 presents the registers used in the UART protocol. Section 5 discusses about results and the Conclusions are presented in section V6.

UART Protocol Overview
In this UART stands for Universal Asynchronous Receiver and Transmitter. The objective of a UART device is transmitting and receiving serial data. In UART communication, there are two UART devices, namely transmitter and receiver. The role of the transmitting UART is to convert parallel data to serial data [3]. The receiving UART again converts the serial data to parallel form. One big advantage is that only two wires are needed for transmission and reception of data between two UARTs [4].
UART is an asynchronous device i.e. it does not have a clock signal to synchronize data. Instead of a clock signal, the data frame consists of start bits and stop bits. On receiving the start bit the UART knows that it has to start reading the bits. The frame structure of UART protocol is shown in Figure 2. After detecting the start bit, at some frequency UART reads the bits is known as Baud Rate. The unit of Baud rate is bits per second .The Transmitter UART and Receiver UART should work on same baud rate. In UART data bus is used to transmit and receive the data. Data is transferred in parallel form the transmitter to receiver. After that, the data frame is created by adding start, stop and parity bit. This data frame is sent serially on Transmit pin. The receiver starts reading the data frame bit by bit at its receiving end. And it is again converted into parallel form by removing star, stop bits [5]. The data which is to be transmitted is arranged into frames. Each Frame carry one start bit, five to nine data bits, parity bit, and one or two stop bits. The actual data length can be five to eight bits. Two modes to do the communication between UARTs:  Half Duplex Mode:-In Half duplex mode the communication is done only from transmitter to receiver which means only in one direction.  Full Duplex Mode:-In full duplex mode two UARTs can transfer data with each other concurrently. There are several advantages of the UART protocol such as:  It is two wired protocol.  Clock signal is not required.  Error detection is possible.

Results
In the work presented here, the data bus width of both the transmitting and receiving UART is 8.

Conclusion
The UART is successfully designed using Verilog HDL and System Verilog. The verification is successfully done using UVM methodology. The UART Protocol functionality has been verified successfully. The different test cases are also implemented. This communications between the two UART devices are seen to be working as per requirement. The UART Receiver is also capable of converting Serial data into parallel data.