Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit

. This paper presents a novel energy efficient logic called Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL) operating using four phase power clock sources. The CSIPGL based circuit is capable of operating through a wider range of frequency from 100MHz to 1GHz. CSIPGL logic has been designed using UMC 90nm technology model files and are simulated using Cadence® Virtuoso EDA tools. Efficiency of CSIPGL circuit is validated by comparing it against CSSAL, SQAL, SyAL, adiabatic logic circuits based on single charge sharing transistor [14] and EE-SPFAL circuit designs. Power consumption of AND/NAND and XOR/XNOR sub modules used in the design of 4-bit Carry Lookahead Adder circuits (CLA) are compared. 4-bit CLA is taken as a benchmark circuit to validate the efficiency of the proposed CSCPAL circuit.


Introduction
In the last few decades, increasing demand in the usage of portable devices such as laptops, mobile phones and tablets have made the researchers focus on development of strategies that can reduce the overall power consumption of circuit. Plenitude of articles are found describing various low power circuit design practices. Conventional CMOS (Complementary Metal Oxide Semiconductor) circuits dissipate more energy during charging and discharging process. Also, the dynamic power consumption is a major concern to be considered as it depends on the switching activity of circuit. Adiabatic logic principle is a non-conventional technique that has the capability to achieve low power dissipation [1]. Adiabatic logic circuits are energized by a power clock source, which acts both as power supply and clock signal for synchronization purpose. This slow varying pulse can be either two phase sinusoidal power clock source or four phase trapezoidal power clock source. Utilization of power clock source in the design aids in constant current flow during charging and discharging processes. Some of the most common adiabatic logic circuits found in the literature are 2N2P [2], 2N2N2P [3], Positive Feedback Adiabatic Logic (PFAL) [4], Differential cascode Pre-resolve and Sence Adiabatic Logic (DCPAL) [5], Pre-resolve Sense Adiabatic Logic (PSAL) [6][7][8] [9][10], Secured Quasi Adiabatic Logic (SQAL) [11], Symmetric Adiabatic Logic (SyAL) [12], Charge-Sharing Symmetric Adiabatic Logic (CSSAL) [13], adiabatic logic circuit based on single charge sharing transistor [14] and Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE -SPFAL) [15]. In this paper, a novel Charge Sharing based Improved Pass Gate Adiabatic Logic (CSIPGL) has been proposed. Performance characteristics of the adiabatic circuits are evaluated by Cadence® Virtuoso simulations using UMC 90nm technology models. 4-bit CLA circuit has been designed to validate the efficiency of the proposed logic. The efficiency of the proposed logic is proven by comparing with single charge sharing transistor based adiabatic logic and EE-SPFAL structures. structures. This paper is organized as follows. Section 2 describes the principle of adiabatic logic, Section 3 explains the operation of CSIPGL, Section 4 depicts the various adiabatic logic designs using CSIPGL and Section 5 presents the results and discussion and Section 6 concludes the paper.

Adiabatic Logic
Conventional CMOS circuits dissipate energy during the charging and discharging of output nodal capacitances through the pull up and pull-down networks. Energy dissipation in CMOS is given by Here, V DD is the supply voltage, α is the switching factor and C L is the output nodal capacitance.

Figure 1. Adiabatic Switching Principle
Energy dissipation in conventional CMOS can be reduced by curtailing any one of the following factors, namely, 1) Reducing the nodal capacitances, 2) Reducing the number of transitions or 3) Supply voltage reduction, which can drastically reduce the energy of CMOS based circuits. However, it also degrades the speed and noise performance of the circuit. These limitations lead to the development of a new-fangled logic called Adiabatic Logic or Energy Recovery Logic, which is a non-conventional low power VLSI design technique. As mentioned earlier, Adiabatic logic utilizes a time varying voltage pulse as its power-clock, while the CMOS counterpart circuits use a constant voltage power supply. Each power-clock signal consists of four different phases of operation, viz. a) Evaluate Phase, b) Hold Phase, c) Recovery Phase and d) Wait Phase. Total energy consumption of an adiabatic circuit is given by where R is the resistance across the charging path and T is the transition time. Figure 1 shows the principle of adiabatic logic.

Proposed Novel Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL)
Operation of the proposed Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL) is presented in this section. Figure 2a and figure 2b depict the logic structure and input-output transients of CSIPGL. Let A and /A be the input and its complementary input signals, OUT and /OUT be the output and the complementary output, PC be the power clock source and CS be the charge sharing signal. Any desired logic function can be implemented in place of functional block (F) and its complementary functional block (/F).  During the WAIT phase, power clock source PC is constant at 0V. Input A slowly increases from 0V to V DD and /A remains at 0V. CS signal is at V DD . When the gate to source voltage of MN2 and MN4 is greater than the threshold voltage of the respective devices, they start to conduct. However, MN5 remains OFF with /A at 0V. During the evaluation phase, input A is HIGH at V DD and /A is at 0V. Power clock source PC ramps up to V DD . CS signal is disabled and hence MN3 is switched OFF. MN2 and MN4 are enabled as A is HIGH and this in turn causes OUT node to be connected with the ground. The voltage at OUT node is LOW which switch on MP2 transistor. During the HOLD phase, power clock PC remains stable at V DD , charging process at the /OUT node continues and /OUT node follows PC.  During the recovery phase, inputs A and /A are at 0V. MN1, MN2, MN4 and MN5 are disabled. The charge deposited in the nodal capacitances of /OUT node are recovered to the PC through MP2 transistor. During the Wait phase of next cycle, when CS is enabled, d epending upon the inputs, either A or /A input is switched ON. The corresponding transistor in the pullup network recovers the left-over charge from the output nodal capacitances to PC and the transistors in the pull-down network provides a path for the trapped charges to ground.

Design of 4-Bit Adiabatic CLA Circuit
The structure of a 4-bit adiabatic Carry Lookahead Adder (CLA) is shown in Figure 3

Design of 4-Bit Adiabatic CLA Circuit
This Section validates the power efficiency of Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL) circuit. UMC 90nm technology models are used for the design and simulation of all adiabatic logic circuits under considerations. Simulation environment considered for simulating circuits is Cadence Virtuoso ® EDA tool. A nodal capacitance of 1Ff is connected at the output nodes while simulating the circuits for emulating the fan-outs. A 4-bit CLA circuit is considered as a benchmark circuit for validating the efficiency of CSIPGL circuit. Average energy consumption of CSIPGL based 4-bit CLA is compared with EE-SPFAL and adiabatic logic circuit based on single charge sharing transistor based 4-bit CLA. Additionally, power efficiency of sub circuit components used in the design of CLA adder such as XOR/XNOR logic and AND/NAND logic are also investigated.  Figure 5 shows the power consumption of AND/NAND gates designed based on CSSAL, SQAL, SyAL, adiabatic logic circuit based on single charge sharing transistor [14] and CSIPGL at an operating frequency of 500MHz with a supply voltage of about 1V. Power consumption of about 841.8nW, 381.2nW, 716.6nW, 174.4nW and 151.7nW is consumed by CSSAL, SQAL, SyAL, adiabatic logic circuit based on single charge sharing transistor [14] and CSIPGL circuits, respectively. Hence, it is clear that CSIPGL circuit is power efficient when compared with the prevailing circuit counterparts.

XOR/XNOR logic gate
XOR/XNOR logic circuit is designed using CSSAL, SQAL, SyAL, adiabatic logic circuit based on single charge sharing transistor [14] and CSIPGL circuits. These circuits are operated at a frequency of 500MHz at 1V supply voltage. Figure 6 depicts the power efficiency of the proposed circuit

4-bit CLA
Brent Kung Carry lookahead adder is designed with the EE-SPFAL, adiabatic logic circuit based on single charge sharing transistor [14] and CSIPGL circuits. These circuits are operated at various frequency from 100MHz to 1GHz with a supply voltage of about 1V. Figure 7 depicts the energy comparison of CLA adder designed using the above said counterparts. EE-SPFAL and adiabatic logic circuit based on single charge sharing transistor [14] are considered for the design of 4-bit CLA as these are the most efficient circuits proposed so far in the literature. It is evident from the results that CSIPGL consumes lower energy than the above-mentioned counterparts. Also, CSIPGL is energy efficient at lower frequency and as frequency increases, the efficiency of CSIPGL is degraded. Hence, CSIPGL is best suited for low frequency applications.

Design of 4-Bit Adiabatic CLA Circuit
This paper validates the efficiency of CSIPGL circuit through the design of arithmetic architectures operating through a wide range of frequency from 100MHz to 1GHz. CSIPGL circuit reduces the floating nodal issues which are prevalent in the existing counterpart designs and thereby increasing the power efficiency. Performance of the proposed circuit is validated by the design of 4-bit carry lookahead adder designs. CSIPGL based 4-bit CLA is 73% and 52% more efficient than EE-SPFAL and adiabatic logic circuit based on single charge sharing transistor circuit operating at 100MHz frequency. CSIPGL circuit is proved energy efficient at low frequencies because of its superior energy recovery characteristics, lower leakage current and reduced number of transistors.