Error correction algorithm developed for special-purpose computing devices based on polynomial modular codes

Special-purpose computing devices (SPCD) are used to solve tasks that require either real-time processing of a large amount of data, including digital processing of audio/video signals and OFDM systems, or high accuracy, like friend-or-foe identification for satellite communications systems. To achieve this goal, it is proposed to use parallel processing at various levels. Parallel computing increases circuit costs though, which incites SPCD to fail. The most promising solution to this contradiction lies in the use of position-independent redundant polynomial modular codes (PMC). These codes aim to increase the speed of data processing through the parallelization of computation at the level of arithmetic operations. What is more, thanks to independent and parallel processing of residues, they have the potential to detect and correct errors caused by the failures to occur during computation and during transmission over communication lines due to interference. Therefore, it is crucial to develop an error correction algorithm for special-purpose computing devices based on polynomial modular codes.


Introduction
Modern special-purpose computing devices (SPCD) have complex architecture. Increased requirements for computation rates have led to stepping up the concept of parallel computing. Parallel computing is widely used in digital processing of audio and video signals [1,2], for a small-scale signal analysis [3], in systems supporting OFDM technology [4], friend-or-foe identification systems [5].
However, parallel computing requires increased circuit costs for the implementation of SPCD. Thus, the following contradiction is evident: on the one hand, constantly growing speed requirements lead to the need for parallel computing, but, on the other hand, this increases the frequency of failures and the off time due to troubleshooting challenges. It is possible to solve this contradiction through an increase in fault tolerance of parallel SPCD. It is proposed in [6] to achieve this goal through the use of failure masking. However, the "2 of 3" method, with its simplicity of implementation, has a significant drawback -major circuit costs.
This drawback can be eliminated with redundant polynomial modular codes (PMC). These codes provide an increased processing speed due to parallelization of computation at the level of arithmetic operations. Moreover, due to independent and parallel processing of residues, polynomial modular codes have the potential to detect and correct errors caused by the failures to arise during computation, and during transmission over communication lines due to interference. Therefore, it is crucial to develop an error correction algorithm for special-purpose computing devices based on polynomial modular codes.

Techniques for code modularity
Modular codes that fall within position-independent codes can be divided into two classes. The first class is based on the residue numeral system (RNS) [8]. For their construction, the system is defined by a set of m integers show that arithmetic operations are performed in parallel, which allows for computations at maximum speed. Therefore, RNS codes are used in digital signal processing [8], digital filtering [9] and multi-scale signal analysis [10,11].
The second group consists of polynomial modular codes. These codes feature prime polynomials Thus, any polynomial W(x), for which Then, for a polynomial modular code )) )) In this case, summation and subtraction are defined by a finite Galois module. In the target case, the Galois field GF (2) was chosen.
Since polynomial modular codes are position-independent, special-purpose computing devices should contain a direct converter from the positional numeral system (PNS) to PMC, as well as an inverse PMC-to-PNS converter. Inverse transformations are generally allowed by the Chinese remainder theorem is an orthogonal basis for PMC; gi(x) -the weight of ith basis is so PMC applications obviously encompass orthogonal signal transformations in telecommunication systems [10], SPN encryption [12], and friend-or-foe identification [5]. Once applied, PMC can not only speed up data processing, but also improve the fault tolerance of special-purpose computing devices based on polynomial modular codes.

Error detection and correction based on the error syndrome in the extended base system
To ensure single-error correction and detection, two parity bases When an error occurs in W(x), the jth remainder where is the error value on jth PMC basis; j = 1, 2, …, n + 2.
Thus, when an error occurs, then The error detection and correction algorithm is based on the projection method in [8]. In this method, residues are sequentially removed from the code A resulting truncated code is transferred to the PNS according to (8). Then the result is compared with Only when the remainder ) x ( w * j is removed, the condition (10) will be satisfied. This way, errors are detected and corrected. The main drawback of the method is large circuit and time costs required for detecting and correcting errors. An algorithm based on the extended base system is a means to eliminate this drawback.
The algorithm formulated is based on the congruence of parity residues that are determined by information residues. To do this, the error syndrome is calculated as , then the PMC combination is not in error. Otherwise, the magnitude of the syndrome can determine the position and value of an error.
To develop the detection and correction algorithm, we use the expression (8) using only n PMC information bases The expression (13) avoids the calculation of the rank rW (x) when performing the inverse transformation. We calculate the parity residues The expressions (14) and (15) show that this algorithm can be implemented in parallel, which reduces the time required to calculate the error syndrome.

Results and discussion
Let the information moduli Let the polynomial be . So the code is not in error.
. Let us use the formulated algorithm. Then . So the code is in error. All single-error noncongruent syndromes were obtained during the study. Then The error has been corrected. The effectiveness of the formulated error detection and correction algorithm and projection method was assessed by modeling based on an Altera processor from the Cyclone III family of the EP3C80F484C6 model. Digital circuits were evaluated against the following criteria: the time of the operation to be implemented on the FPGA and the number of FPGA logical elements (LE) exploited. The studies show that for one inverse transformation from PMC to a positional code to be implemented, circuit costs will be 1049 LEs, and span time -26.83 ns. Since in the considered example five bases are used, five inverters are also required, the circuit costs of which amount to 5245 LEs. In this case, the above algorithm required 945 LEs, and 24.57 ns. Thus, the formulated error detection and correction algorithm based on the extended base system reduces circuit costs by 5.55 times and span time by 1.09 times compared to the projection method.

Conclusion
The paper presents an algorithm for detecting and correcting errors, based on the extended PMC base system. To evaluate its effectiveness, the above algorithm was compared with the projection method. An Altera processor from the Cyclone III family of the EP3C80F484C model was selected for simulation. A comparative analysis showed that the projection method implemented for the selected example required five inverse PMC-to-PNS converters. Thus, the formulated error detection and correction algorithm based on the extended base system reduces circuit costs by 5.55 times and span time by 1.09 times compared to the projection method.

Acknowledgments
This work was supported by the Russian Foundation for Basic Research, project No. 18-07-01020.