Abstract
Josephson-junction based technologies, such as RSFQ, are receiving growing investments due to their high speeds and low power.
As the time interval between the data input and the clock becomes smaller, clock-to-Q delay of a flip-flop increases. In conventional timing analysis, setup time is defined as the interval where clock-to-Q delay increases by 10%. This allows the pipeline to be divided into separate stages and STA to be performed independently for each stage.
However, since RSFQ is pipelined at gate-level, setup time is a significant portion of the clock period and makes this timing constraint extremely conservative. Instead, we define setup time based on the probability of causing a logic error and develop a new STA method that allows larger increases in clock-to-Q delay, i.e., timing bleed, whenever the data input arrives late. We present results of simulations for benchmark circuits with process variations to demonstrate that our new method certifies much higher speeds for RSFQ logic.
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