Serial communication protocol for FPGA-based systems

The article presents results of development of communication protocol for UART-like FPGA-systems. Developed communication protocol supports asynchronous oversampled signal transmission, with 4b/6b encoding for DC-balance maintaining. Algorithm of CPLD-based receiver of signals forming by this protocol is described. This development is relevant for the task of continuous transmission of several control signals over a fiber-optic line, when the use of ready-made UART devices is unjustified. The presented protocol and algorithm are easily implemented on the FPGA and can be used in devices where it is important to minimize the number of elements used. Also, the protocol contains encoding that allows the transmission of low-frequency signals along a line with DC-coupling.


Introduction
In the infocommunication system it is often necessary to make asynchronous data transmission. The node of digital devices that provide such a transmission is called universal asynchronous receivertransmitter (UART) [1]. To transfer data through such a node, special data transfer protocols (for example, Ethernet or RS-232) are created [2]. Transmission occurs by serializing data and creating a message according to a specific protocol, which is transmitted to the receiver.

Figure 1. Typical message chart for UART protocols
In addition to standard solutions, various private solutions are being developed, both for the implementation of standard protocols and for their modification. For example, various tasks on the implementation of UART on FPGAs are discussed in [3][4][5], the use of FPGAs for operation by the physical Ethernet layer is discussed in [6][7][8]. As we can see, there are many different developments in implementing UART systems on FPGAs so this is actual task nowadays.
In this work, the problem of transmitting several signals over an optical line with an SFP interface was solved. To do this, these signals must be appropriately encoded on the transmitter side and then restored to the receiver. The RS-232 protocol is not suitable for this task, since due to transmission over the fiber optic line it is necessary to provide the same number of zeros and ones for DC coupling  [9]. For our task, you can use the Ethernet protocol and the corresponding turnkey solutions on the FPGA, however such a solution would be redundant, since the Ethernet protocol is designed to transfer a large amount of data to the CPU, which makes the protocol and the device itself more complicated, it requires the use of an FPGA with a large number of logic elements operating at high frequency. At the same time, to solve our problem, you can create a special data transfer protocol, which will reduce the requirements for the device. In particular, instead of standard FPGAs, you can use CPLDs (Complex Programmable Logic Device) that contain a small number of logical elements and have internal memory. Another difference is that Ethernet is designed to receive packets of data that arrive at different times, which makes it necessary to control the flow of data. In our case, the messages are transmitted continuously, which creates its own specifics of the operation of the device. For example, an under / overrun problem, when the processor does not have time to read the information or when the processor processes the information too quickly -there is no such problem in the FPGA device, so messages can be sent continuously.
Summary, the development uses some ideas of popular protocols to create a special protocol for asynchronous continuous information transfer. Also, serialization algorithm was developed so we can transfer several discrete signals with this protocol. For example, such a system can transmit several meanders of different frequencies on a single fiber optic link.

Materials and methods
The developed protocol was based on known UART protocols. Then programs were written in the Verilog language in the ISE Design Suite for the FPGA for the transmitter and the receiver, in which was laid the algorithm for creating the parcels and for their decryption. Checking the code was carried out in the simulator and then on the assembled device. The device was based on CPLD Xilinx XC2C256 FPGA, a 100 MHz oscillator and a SFP transceiver for transmitting information via fiberoptic links. Evaluated the stability of the algorithm, restrictions on the frequency of transmission. To track the stability of the work, an error tracking algorithm was provided.

Results
As a result, a data transfer protocol was obtained, which provides asynchronous continuous data transfer and an FPGA algorithm was created for transmitting and receiving data using this protocol. The following is a message chart and waveform of signal formed by this protocol:  Unlike, for example, the RS-232 protocol, a sync word of a fixed length is added here instead of the idle state. The receiver performs synchronization by tracking the change in the signal level, that is, on the signal front. Each bit is transmitted several times -thus providing stability to the difference between the clock frequencies of the receiver and transmitter (simulation has shown that the difference can reach units of percent). Number of bits in sync word should be bigger than number of data bits so receiving system can always determine where data is and where is a sync word. This condition can be defined as Since the algorithm was developed for a low-frequency device, the DC coupling problem arises, so coding was used. Developed encoding based on 8b/10b encoding ideas, that shown in [9]. Since we're using continuous data flow we don't need algorithms for running disparity control. Table for "4b/6b" encoding is shown below. The idea of this encoding is to put any of 4-bit word to one-to-one  (2) where signal N is number of bits before encoding. Expression in brackets in (2) should be even. At the source of the message and the receiver, the clock frequency may be slightly different. Oversampling is used to fix this problem. Each bit is transmitted several times, that is, the duration of each bit is increased a certain number of times. This reduces the transmission rate, but it simplifies the synchronization of the transmitter and receiver. In the developed algorithm, the receiver reads the input state from the middle of the bit and synchronizes on the signal front. During the simulation, it was found that the frequencies of the receiver and transmitter can differ by a few percent. Similar results are presented in [10]. According to this paper, we have formula for maximum period error: For oversampling ratio 10 S  and 6 data B  we have max 6.67%.  For example, ASDM oscillators, which we used in experiment, have 100 ppm frequency stability [11].
Overall length of message can be calculated by next formula: T is length of oscillator period, S is number of samples (oversampling multiplier). From (4) we have expression for sampling frequency: Receiver was implemented on CPLD. The Verilog consists of if-else and case statements. Sample counter for oversampling, shift register and output register are provided in the device. The input sequence is written to the shift register, and if its contents match one of the values in Table 1, the corresponding value is written to the output register. Information about the resources required by the implementation of the algorithm on CPLD XC2C256-7TQG144C is given in Table 2.

Discussion
With the help of the obtained algorithm, it was possible to realize the continuous transmission of several digital signals along one line. Naturally, the transmitter clock frequency must be higher than the frequency of the transmitted signals. The exact maximum limit for the periods of transmitted signals is indicated in the formula: Also, we can calculate the spectrum efficiency [12,13]: where R is a bit rate, F  is a bandwidth determined by sampling frequency. From (4) we have: which simply means that spectrum efficiency is equal to number of transmitted bits in one message. But we should remember that increasing the number of signal bits lead to increasing the length of message and decreasing the sampling frequency.

Conclusion
A data transfer protocol was obtained that provides asynchronous continuous transmission of several data streams over a fiber-optic line and an algorithm for an FPGA for transmitting and receiving data using this protocol was created. A table has been developed for 4b / 6b coding. Expressions for protocol parameters was shown. The resulting algorithm was successfully tested in the simulator and on the assembled device.
The protocol is intended for systems where it is necessary to transmit several signals over a single optical line. The resulting protocol is quite simple to implement on CPLD, which simplifies the creation of a device for working with this protocol.