65-nm CMOS element of matching for content-addressable memory resilient to impact of single nuclear particles

65-nm CMOS element of matching for content-addressable memory resilient to impact of single nuclear particles is proposed. Element includes upset-hardened STG DICE memory cell and XOR logical gate based on two tristate inverters. Transistors of the element are separated into two identical joint groups spaced on the chip by distance of more than 4 μm, which practically excludes the possibility of cell upset under impact of single nuclear particles. Designed element of matching is implemented in resilient to single event effects translation lookaside buffer of microprocessor.


1.
Introduction Content-addressable memory (CAM) [1] is used for parallel high performance processing of data streams. Elements of matching for content-addressable memory are conventionally designed on base of CMOS 6-transistor (6T) memory cells, which have increased sensitivity to the effects of single nuclear particles impact [2]. For today, there are a few upset-resilient designs of ternary contentaddressable memory [3]-[4], however, they were not used in practice.
Fault-tolerant DICE (Dual Interlocked Cell) memory cells [5] were an effective decision, but with the technology scaling to 65 nm and less, they lost their advantages over 6T cells because of decreasing of distance between mutually sensitive nodes of the cell [6]. In STG DICE (Spaced Transistor Groups DICE) memory cells [7] the transistors are separated into two groups that are spaced on the chip, so the impact of single nuclear particle on only one group does not lead to a failure of the cell [8]. Device simulation results [9] and experimental results [7] proved an increased tolerance of STG DICE memory cells to single event effects compared to 6T and traditional DICE memory cells. In this work, the design of the element of matching for content-addressable memory based on STG DICE memory cell is proposed [10].

2.
Structure of the element of matching Element of matching includes STG DICE memory cell and the logical gate "Exclusive OR" (XOR), which consists of two tristate inverters TRInv 1 and TRInv 2. Figure 1 presents the scheme of the element of matching. Element of matching stores one bit of information and compare the stored bit with the sequence of bits from Input 1 and Input 2. Input 1 provides data in normal form, and Input 2 provides data in inverse form.
Bit of data is written to the STG DICE memory cell that have two steady states: ABCD = 0101 (storing of logical "0") and ABCD = 1010 (storing of logical "1"). If a single nuclear particle impacts on only one group of STG DICE, the cell does not upsets, but only goes to one of the unsteady states: Comparison of information bits is produced by the XOR gate. Output state of XOR gate is determined by the logical function: where X AC = X A = X C is the logical levels on the nodes А and С that are the same in steady state of STG DICE, X BD = X B = X D is the logical levels on the nodes B and D that are the same in steady state of STG DICE, X IN1 is the normal logical level of input bit on Input 1; X IN2 = nX IN1 is the inverse logical level of input bit on Input 2; Y OUT is the output logical level of XOR gate.
Transistors of element of matching are separated into two joint groups, every joint group includes one group of STG DICE memory cell and one tristate inverter (a half of XOR gate). Single nuclear particle impact on the transistors of XOR gate induces the noise pulse on the output of XOR [11]. Impact of particle with linear energy transfer on its track up to 40 MeV•cm 2 /mg can be simulated with When transistors of one group of STG DICE collect an induced charge, the cell goes to the unsteady state, and the output of XOR gate goes to the high-impedance state or to the state with lowlevel output voltage b•V DD [12]. Figure 2b presents the node voltages of element of matching depending on time when STG DICE goes to the unsteady state ABCD = 0011. Output voltage of element of matching takes on value b•V DD = 170 mV (dashed curve on figure 2b).
Placing the transistors of tristate inverter with the transistors of STG DICE group on the chip together in one joint group creates a possibility of simultaneous impact of induced charge on these transistors. In this case, the compensation of output noise pulse is possible. The output voltage of element of matching depending on time under the impact of current pulse on the output of element in unsteady state of the cell ABCD = 0011 is shown on figure 2b with the green curve. Simultaneous charge collecting by the transistors of STG DICE group and transistors of tristate inverter may lead to decreasing of output noise pulse amplitude.

3.
Topology of the element of matching Transistors of the element of matching are separated into two identical joint groups spaced on the chip. Basic variant of topology of two elements of matching is presented in figure 3. On the chip, area between two joint groups of every element is filled by one joint group of another neighboring element. This interleaving provides the distance between mutually sensitive nodes of every element of matching of more than 4 µm with minimum area overhead. The shaded areas on figure 3 are the drains of closed transistors of STG DICE memory cell in steady state ABCD = 1010. where H J.G and W J.G are the height and width of the joined group; N TR is the number of transistors in the joint group; I OUT.LEAK is the leakage current of the output of tristate inverter; t DEL is the delay of XOR gate output signal at the load capacitance of 2 fF. Table 2 presents the values of distances between mutually sensitive nodes of STG DICE memory cell in state ABCD = 1010. In inverse logical state ABCD = 0101 another couples of transistors are sensitive to particle impact, but the values of distances between them are the same. The interleaving of joint groups of neighboring elements provides the distance between mutually sensitive nodes of every element of more than 4 µm. It makes the element of matching resilient to impacts of single nuclear particles with linear energy transfer on its track up to 70 MeV•cm 2 /mg [11]. Guardian rings are placed along the boundary of p-bulk and nwell for protection against latch-up effect. Common for this technology parameters of topology are: the depth of p-bulk is 3 µm, p-bulk doping concentration is 10 16 cm -3 , device layers are Gaussian

Implementation in translation lookaside buffer
Presented element of matching is implemented in content-addressable memory block of translation lookaside buffer (TLB) of microprocessor [13]. Floorplan of designed TLB is presented in figure 4. The main functional blocks of TLB are: block of content-addressable memory (CAM), block of random access memory (RAM), block of read and write buffers (R/W BUF), block of input address decoder (DEC), block of output address encoder (ENCOD) and block providing control and synchronization signals (CONTROL). In presented TLB, capacity of CAM block is 64×47 bit and capacity of RAM block is 64×59 bit. Table 3 presents the parameters of content-addressable memory block designed on base of proposed element of matching. Here H is the height of the block, W is the width of the block, S is the area of the block, N TR is the number of transistors in the block, V DD is the supply voltage, F CLK is the frequency of clock signal, P WRITE , P SEARCH , P READ are the power consumptions in write, search and read modes. Figure Figure 4. Topology of translation lookaside buffer based on hardened elements.

Conclusion
The design of 65-nm CMOS element of matching for content-addressable memory based on upsethardened STG DICE memory cell is proposed. Transistors of the element are separated into two identical joint groups, and interleaving of joint groups of neighboring elements provides spacing of STG DICE mutually sensitive nodes on the chip by distance of more than 4 µm. Proposed element of matching is implemented in translation lookaside buffer resilient to single event effects. Proposed design is promising for microprocessor systems with increased resistance to impacts of single nuclear particles.