The Front-end for the new focal plane detector for the NUMEN project

The design of the front-end electronics for the new tracker of the MAGNEX Focal Plane Detector (FPD) for the NUMEN project is presented. The front-end is based on the VMM chip, developed for ATLAS experiment at CERN. The architecture of the front-end (FE) electronics is designed to be modular and scalable to the final detector. The segmented anode board is designed in order to take advantage of the unique performances of the VMM chip, allowing a digital reconstruction of the track at high event rate. This anode board is connected to front-end by mean of Micro Coax Cable Assembly and does not make use of vacuum connectors. The front-end boards will be placed in air, facilitating in this way the heat dissipation and the connection to the read-out (RO) electronics. An innovative anode read-out strategy allows the reduction of the total number of channels to about 1400 and the measurement of the track at different depth in the detector with 750 µm spatial resolution.


Introduction
The foreseen upgrade of the Superconducting Cyclotron of INFN-LNS to reach the high beam intensity necessary for the NUMEN [1,2,3,4] experimental program demands substantial changes in the technologies used for the MAGNEX [5,6,7] Focal Plane Detector (FPD) [8] together with new frontend electronics. The design of front-end (FE) and read-out (RO) electronics was conducted in parallel with the design of the new FPD. In particular, one of the main objectives was to design a modular, scalable, radiation hard architecture, which, in addition, fulfilled the strong requirements in terms of high event rate, easy maintenance and precise synchronization.
The FPD tracker was radically redesigned taking advantage of the possibility to design a brand new full-custom FE and RO electronics.
A new concept for the tracker was developed. The starting point was to extract, for each track, the position of the ions in the volume of the tracker in a fully digital way.

The New Focal Plane Detector
The ionization charge is driven by an electric field in the gas towards a multiplying stage, typically a triple GEM or THGEM. Then the electrons are directed towards a first layer of 750 µm pitch strips.
Each strip of this layer is capacitive coupled to a twin strip in a second layer. The charge pulse inducted in the twin strip is then integrated by the FE and shaped.
The shaped signal is compared to a suitable threshold and the logic output of the comparator identifies the hit strip.
In this scenario the position is extracted by only one strip without the need for the calculation of the center of mass.
The value of the capacitance for each channel of the tracker is optimized to ensure maximum chip resolution in terms of charge and time. The drift time is also measured by the FE at sub-ns resolution.
An innovative scheme for the connection of FE electronics to the anode board was developed. The main objective was to place the FE in air to simplify the heat dissipation, the maintenance and, above all, the interconnections to RO. An advantage of this strategy is also the possibility to adopt countermeasure against to high level of radiation during the experiment.
The working principle of the segmented readout board of the new FPD tracker is represented in figure  1.

Design of the FPD
The FPD board has been designed in such a way as to cover the active area of the GEM foil.
This board is made up of 4 layers the first consists of a power supply plane in such a way as to be able to apply a potential difference to align the lines of the electric field, the second is the routing plane of the coupled strips, the third is the layer in which are present the strips exposed to the gas and finally the fourth layer is the ground plane in which there are trenches.
In figure 2 shows the presence of tranches that are transversal to the strips and identify the area in which the charge is collected so as to reduce the number of collisions on the individual strips.

The Front-End
The design of the front-end electronics for the new tracker of the NUMEN Focal Plane Detector is presented. The front-end is based on the VMM chip [9], developed for ATLAS experiment at CERN.
The architecture of the front-end electronics is thought to be modular and scalable to the final dimensions of the detector. The segmented anode board was designed in order to take advantage of the unique performances of the VMM chip [10], allowing a digital reconstruction of the track at high event rate.   3 shows the architecture of the VMM3, which is the actual evolution of VMM1, but with a much higher complexity and functionality. Each of the 64 channels provides the peak amplitude and time with respect to the bunch crossing clock signal or other trigger signal in a data driven mode. This is accomplished as follows. Each channel is equipped with a fast comparator with an individually adjustable threshold. When a signal crosses a set threshold a peak detection circuit is enabled.
Neighbour-enable logic allows setting the threshold relatively high and yet recording very small amplitudes. At the peak a time-to-amplitude converter is started and stopped by the trigger signal. The two amplitudes are digitized and stored in a de-randomizing buffer and readout serially with a smart token passing scheme that only reads out the amplitude, timing, and addresses of the channels with information, thus dramatically reducing the data bandwidth required and resulting in a very simple readout architecture.
The VMM3 has 64 channels easing the handling of a large number of channels. It also provides prompt information that can be used to provide pre-trigger signals.

Mode continuous
In the Numen experiment, the chip will be used using continuous mode. The ASIC can operate in three modes: direct-outputs, two-phase or analog and continuous or digital.
In continuous (digital) mode a total of 38 bits are generated for each event in the VMM3. The first bit is used as a readout flag, the second is the threshold crossing indicator (it allows discrimination between above-threshold and neighbour events). Next is a 6 bits word for the channel address, followed by 10 bits associated with the peak amplitude, and 20 bits associated with the timing.
The 38-bit word is stored in a 4-events deep de-randomizing FIFO (there is one FIFO per channel) and it is read out using a token-passing scheme where the token is passed first-come first-serve only among those FIFOs that contain valid events. The first token is internally generated as needed and advanced with the token clock signal. The data in the FIFOs is thus sequentially multiplexed to the two digital outputs data0 and data1. The first output data0 is also used as a flag, indicating that events need to be read out from the chip. The external electronics releases a sync signal using the token clock as well (i.e. the token clock provides both advancement and data output synchronization), after which the 38-