Performance enhancement by an improved compact design for self-powered synchronous switching harvesting circuits

In the self-powered synchronous switching circuits, the electronic beakers for producing the desired switching control signal consumes a significant part of harvested energy. Moreover, the capacitors used in the electronic breakers brings the effect of decreasing the electromechanical coupling level thus hinders the available power. In this paper, a novel circuit design by combining two separate electronic breaker into a unified one in which only a single capacitor is required and the introduced parasitic capacitance is cut to half. Besides, the diodes in the envelope detectors are also removed. Consequently, both performance enhancement and cost reduction are achieved with this new circuit.


Introduction
Interface circuit is an important part of the piezoelectric generator and will significantly affect the performance. The synchronous switching circuits, such as SSHI (Synchronous Switching Harvesting on an Inductor) [1], SECE (Synchronous Electric Charge Extraction) [2], OSECE (Optimized SECE) [3] and so on, are considered as effective approaches for enhancing the generator's performance in the case of low electromechanical coupling level and providing better adaptability for load variations. A critical issue for these synchronous switching circuits is the self-powered realization. Various methods including electronic breaker [4][5][6], velocity control [7] , mechanical switches [8][9][10], integrated control circuits [11] etc. were proposed. Among them, the electronic breaker possesses the advantage of simplicity and reliability. Generally, a part of the extracted energy from the generator is consumed by the electronic breaker. Moreover, the parasitic capacitance in the electronic breaker, mainly referred to the envelope detector capacitance, imposes an equivalent effect of connecting a parallel capacitor of several times the parasitic capacitance to the generator, thus decreasing the coupling level, especially for the generators with small intrinsic capacitance. Consequently, the generator's performance degenerates in contrast with the ideal case.
Reducing the components of the self-powered circuit components while keeping the function could save the energy consumption and would be helpful to the performance. Recently, an alternative SSHI self-powered design has been proposed with fewer diodes used and better performance [12]. However, two capacitators are still used in the circuit for peak detectors. Compared with the diodes, the capacitance plays a more critical role in the by introducing the switching phase lag and decreasing the coupling level.
In this paper, we propose a simpler and more efficient circuit breaker for synchronous switch techniques dedicated to piezoelectric vibration energy harvesters. In comparison with the regular electronic breaker design for the SP-OSECE (Self-Powered OSECE) [6], this new CSP-OSECE (Compact SP-OSECE) circuit multiplexes the comparator in the envelope detector instead of the diode. More important, only a single capacitor is used for both positive and negative peak detection. The parasitic capacitance of the electronic breaker is thus reduced to half so that the performance is improved. Fig. 1 (a) presents the regular SP-OSECE design with the usual electronic breaker. In the circuit, the piezoelectric element is represented by an equivalent current source i eq =a 0̇ in parallel with an intrinsic capacitance C 0 and a leakage resistor R 0 . Here, a 0 is the piezoelectric force factor and u is displacement of the piezoelectric generator. Two separate envelope detectors are used for determining the positive and negative piezoelectric voltage peak respectively. Each envelope detector is composed of an filtering RC network (R pi an C pi ) and a diode D pi . In addition, a PNP transistor T p1 is used as the comparator for the positive breaker and a NPN transistor T p2 is used as the negative comparator. At the beginning of the positive half-period, both switches S 1 and S 2 are opened which C 0 is charged by i eq with the piezoelectric voltage V p increasing. Meanwhile, C p1 is charged through R p1 and D pi with V cp1 follows V p while C p2 is charged through R b2 and T p2 as well. After V p reaches the maximum value and starts to decline, V cp1 keeps this maximum value. As V p decreases further, the comparator T p1 conducts and output the switching control signal to turn on S 1 . Consequently, the voltage inversion is started in the form of LC oscillation (L 1 and C 0 ). When the induced voltage on L 3 at the secondary side of the transformer is higher than the load voltage V load during the voltage inversion process, the energy stored on the transformer is transferred to the load. Afterwards, similar operations happens for the negative half-period. Clearly, in the regular electronic design, the current source i eq has to charge C 0 , C p1 and C p2 together. Consequently, the piezoelectric voltage V p in the positive half can be approximated as 1 1

Principle and analysis
in which a 1 =a 0 C 0 /(C 0 +2C p ) is the modified piezoelectric force factor with C p1 =C p2 =C p , t 1 is the start time of the positive half-period and T is the period. It can be inferred that the piezoelectric force factor a is decreased to a 1 by C p1 and C p2 . In order to enhance the performance, the CSP-OSECE is proposed with a more compact design as seen in Fig. 1 (b). Instead of two separate electronic breakers, a unified one is constructed for both positive and negative half-periods with a single capacitor C p . Moreover, the comparator transistor T p1 of the positive half-period is multiplexed for not only producing the switching signal but also rectifying the current instead of the diode D p2 in Fig. 1 (a) while T p2 covers the function of D p1 in the negative half-period as well. Two friction diodes are plotted with dotted lines in Fig. 1 (b) to indicate the multipurpose usage of the comparators. The current source i eq charges C p through T p2 and R b2 in the positive half-period and reversely charge C p through T p1 and R b1 in the negative half-period. Both positive and negative voltage peak are reserved on the same capacitor while the comparators works similarly to detect the peak position as before. Fig. 2 presents the voltage waveforms and the switching signal of the two circuits. Easy to find, the CSP-OSECE circuit works the same as the regular SP-OSECE circuit in Fig. 1 (a) with fewer components. Moreover, due to the single capacitor configuration, we can write down the piezoelectric voltage in the positive half-period as 1 1 in which a 2 =aC 0 /(C 0 +C p ).
By comparing eq. (1) and eq. (2), it is found that a 2 is larger than a 1 , which means that better power performance is expected. It is also seen in Fig. 2 that the CSP-OSECE obtains higher load voltage than the regular SP-OSECE does.

Results
In order to verify the performance, a piezoelectric generator is subjected to both SP-OSECE and CSP-OSECE circuits as shown in Fig. 1 (c). The generator's parameters have been identified as follow: C 0 =14nF, a=3.1e-3N V -1 and M=0.006kg. Here, M is the inertial mass. The resonant frequency is measured to be 41Hz in the short-circuit case. In addition, the envelope capacitance C p is selected to be 1.75nF for both circuits and R b is set to 3.3kΩ. The value of C p is selected to obtain the optimal power performance of the circuits. The constant displacement case is firstly investigated with the magnitude of u fixed as 1.25mm and the excitation frequency is selected to be 41Hz at the resonant frequency. Fig. 3 (a) shows the power results of the two circuits. Clearly, the load dependence properties of the two circuits is close to each other while the optimal power is obtained around 470kΩ in both cases. However, the CSP-OSECE obtains much better performance than the SP-OSECE except the small load case. A maximum power of 0.301mW is obtained for CSP-OSECE with a power increase of 30% in consideration that the SP-OSECE circuit has a maximum power of 0.233mW.
The test with a constant acceleration amplitude of 0.5g was also performed with the optimal load of 470kΩ from 20Hz to 60Hz with the power plotted in Fig. 3 (b). Similar to the constant displacement case, the CSP-OSECE circuit always shows better performance. A power boost of 38% is found around the resonant frequency. Moreover, wide bandwidth is also obtained with the CSP-OSECE circuit.

Conclusion
A compact design of the self-powered synchronous switching circuit is proposed in this paper. Compared with the regular SP-OSECE design, the new CSP-OSECE circuit brings two improvements: First, the parasitic capacitance is reduced to half; Second, the circuit has fewer component by excluding the envelope detector diodes. The former improvement is especially useful about the enhancement of the power performance. It is validated by experiments in both constant displacement and constant acceleration cases. Meanwhile, the latter one saves the cost and also assembling space.