SEMICONDUCTOR INTEGRATED CIRCUITS

A new algorithm of inverse lithography technology for mask complexity reduction

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2012 Chinese Institute of Electronics
, , Citation Li Yanghuan et al 2012 J. Semicond. 33 045009 DOI 10.1088/1674-4926/33/4/045009

1674-4926/33/4/045009

Abstract

A new complexity penalty term called the global wavelet penalty is introduced, which evaluates the high-frequency components of masks more profoundly by applying four distinctive Haar wavelet transforms and choosing the optimal direction on which the highest frequency components of the mask will be removed. Then, a new gradient-based inverse lithography technology (ILT) algorithm is proposed, with the computation of the global wavelet penalty as the emphasis of its first phase for mask complexity reduction. Experiments with three typical 65 nm flash ROM patterns under existing 90 nm lithographic conditions show that compared with the gradient-based algorithm, which relies on the so-called local wavelet penalty, the total vertices of the three results created by the proposed algorithm can be reduced by 12.89%, 12.63% and 12.64%, respectively, while the accuracy of the lithography results remains the same.

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10.1088/1674-4926/33/4/045009