The isolation feature geometry dependence of reverse gate-leakage current of AlGaN/GaN HFETs

Reverse gate-leakage current of AlGaN/GaN heterojunction field-effect transistors (HFETs) realized on array of submicron sized fins and conventional mesa isolation feature geometries is investigated at room temperature and zero drain-source bias. For each of the abovementioned device categories, the significance of leakage from the top surface gate as well as gated etched GaN surfaces, especially sidewalls, is studied for a wide range of gate-source voltages (VGS) (i.e. below and above the threshold voltage). It is proven that in the explored fin-type HFETs, for all values of VGS leakage through the gated GaN surfaces, especially the sidewalls, is more significant than the leakage from the top surface gate. This is while in the mesa category, the sidewall leakage is of importance only at less negative values of VGS, and leakage from the top surface gate substantially takes over at more negative VGS values. The discrepancy in the dominance of the aforementioned leakage paths at more negative VGS values among the explored fin and mesa-type HFETs is demonstrated to be due to the stronger electric field across the barrier in the gated region of the mesa-type HFET for this range of VGS. While in the explored fin-type HFETs Ion/Ioff ratio is as high as 2 × 107, the total amount of reverse gate-leakage at all values of VGS is substantially larger compared to the mesa category sharing an equal value of the overall gate width, which substantiates the significance of leakage through etched GaN surfaces in devices composed of larger number of sidewalls, incorporating larger area of gate-overlapping etched GaN surface.


Introduction
AlGaN/GaN heterojunction field-effect transistors (HFETs) have been widely used over the past two decades in power electronics and RF applications. However, problems such as excessive reverse gate-leakage [1][2][3] still hamper their full-scale commercialization. In order to understand the origin of the reverse gate-leakage in these HFETs, several mechanisms have been investigated so far [4][5][6][7][8], which depending on the bias and temperature conditions, the pertinence of these mechanisms in describing the leakage behavior might differ. For instance, in polar III-nitride HFETs for large negative values of gate-source bias (V GS ), due to the presence of a strong electric field across the barrier, Fowler-Nordheim (FN) tunneling has been demonstrated to be the dominant leakage mechanism [6,[8][9][10]. This is while thermionic field emission (TFE) is expected to take over when the electron temperature is also sufficiently elevated [4,5]. When the electric field across the barrier and temperature are not sufficient for FN or TFE, other mechanisms such as Poole-Frenkel (PF) emission or trap-assisted tunneling (TAT) that rely on the existence of traps are observed to be dominant in the evaluation of the reverse gate-leakage [4,7,11,12]. Surface leakage which is associated with the surface traps is another leakage mechanism that becomes significant for large V DS (drain-source) and V GS values [13].
In addition to the leakage through the AlGaN barrier, leakage between the gated sidewalls of the isolation features and the 2D electron gas (2DEG) has been also demonstrated to be worthy of consideration [6,[14][15][16][17]. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.
less negative values of V GS , gate-leakage is smaller in conventional mesa HFETs compared to devices with the same overall gate width but comprising of fin-type isolation features. They have justified this observation by substantiating the dominance of leakage at the gate-covered isolation feature sidewalls over the leakage through the AlGaN barrier at less negative values of V GS [6,14]. They have also attributed the lack of substantial difference between the values of I G for more negative values of V GS among these devices to the significance of leakage through the equally wide barrier of the explored devices over the sidewall leakage for this latter range of V GS [6].
Kováč et al [15] have investigated the gate-leakage of the planar and mesa-isolated AlGaN/GaN HFETs and demonstrated that while the gate-leakage is almost identical for both device categories at more negative values of V GS , at less negative values of V GS it is higher for the mesa-isolated HFETs. They have attributed this higher amount of gate-leakage of the mesa-isolated HFETs to the dominance of the leakage through the GaN buffer and/or the gated sidewalls. On the other hand, Liu et al [16] have shown that placing oxide spacers on the mesa sidewalls act as an insulator between the gate metal and the 2DEG channel and can effectively reduce the reverse gate-leakage of the mesa isolated HFETs. In this approach, unlike the passivation techniques in which the dielectric material is placed also under the top surface gate metal, the oxide spacer is positioned only under the sidewalls' gate metal, which substantiates the leakage from the gated sidewalls to the channel and not the leakage through the GaN buffer. While existence of the leakage through the gated sidewalls has been already investigated in a number of reports, the important correlation between the geometry of the isolation feature and the degree of significance of this leakage path has attracted limited attention [6,14].
Due to the importance of fin-technology as a successful alternative for the realization of high breakdown voltage enhancement-mode transistors [18,19], in this manuscript the relevance of isolation feature geometry to the reverse gate-leakage is investigated over AlGaN/GaN HFETs realized not only on the conventional mesa configuration but also on the fin-type isolation features which are more than one order of magnitude narrower than those studied in [6]. We demonstrate that when the fin dimensions are shrunk to the sub-micrometer range, in addition to gate voltages greater than the threshold voltage (V th ), gate current is dominated by the leakage through the GaN etched surfaces including gated sidewalls for V GS < V th . Accordingly, by investigating the effect of isolation feature geometry on the profile of the electric fields responsible for the leakage through sidewall and top surface gate, we present mechanisms that explain the room temperature leakage characteristics of HFETs realized on micron and sub-micron size isolation features at V DS = 0 V.
Fabrication process, layer structure and the dimensions of the HFETs explored in this work are presented in section 2. Section 3 presents the experimental/simulation results and the analysis. The conclusion is provided in section 4.

Device fabrication and specifications
In this work we used a Ga-face Wurtzite Al 0.25 Ga 0.75 N/GaN heterostructure with an epitaxial layer structure consisting of a 25 nm unintentionally doped (UID) barrier, a 250 nm GaN channel, and a 1.45 μm Fe-doped GaN buffer layer grown on a 4-inch 4H-SiC substrate.
The device processing for realization of the transistors depicted in figure 1 was carried out at McGill University's Nanotool Microfabrication facilities, involving the use of ma-N 2403 negative resist and electron beam lithography (EBL) with a beam energy of 20 keV to define the mesa and fins. The sample was then developed in ma-D 525 and etched using magnetically-enhanced reactive ion etching (MERIE) with Cl 2 /Ar plasma to a depth of 200 nm. The Ohmic contacts were defined using a second EBL step with MMA(8.5)MAA-EL11/PMMA-A2 co-polymer positive resist, followed by immersion in HCl solution to remove the native oxide and Ohmic metallization using NEXDEP e-beam evaporation and lift-off in acetone. The metal stack of Ti/Al/ Ni/Au (20 nm/140 nm/55 nm/45 nm) underwent rapid thermal annealing (RTA) at 830°C for 30 s in Nitrogen environment using JetFirst 200 to form the alloyed Ohmic contact to the 2DEG. The contact resistance (Rc) and sheet resistance (R sh ) obtained through transfer length measurement (TLM) consistently demonstrate the high quality of the fabricated Ohmic contacts, with values of about 0.78 Ω.mm and 400 Ω , −1 , respectively. To define the gate contacts, the third EBL step was performed under the same conditions as the previous one. To prevent e-beam divergence caused by the accumulation of electrons due to the presence of the insulating SiC substrate, DisCharge H 2 OX2 anti-charging agent was used during the second and third EBL steps. Afterwards, a Ni/Au (20 nm/20 nm) metal stack was evaporated using e-beam and lifted-off to create the Schottky gate electrode. Note that surface passivation was not carried out in this reported process.
After the contact pads were deposited, the fabricated AlGaN/GaN HFETs were characterized at room temperature using the SÜSS MicroTec PM5 probing station and Keithley 4200-SCS semiconductor characterization system.
In order to investigate the effect of isolation feature geometry on the reverse gate-leakage of AlGaN/GaN HFETs, we have fabricated HFETs realized on two different isolation features including conventional mesa and fin structures (figure 1) in which cases the channel width is 44 μm and 0.4 μm, respectively. The HFETs of the fin-type consist of three fins that are 0.4 μm wide, therefore the overall gate width in the fin category is 1.2 μm. All of the fabricated devices have a gate length (L G ) of 0.6 μm, gate-source spacing (L GS ) of 2.4 μm, and gatedrain spacing (L GD ) of 3 μm. As shown in figure 2, the threshold voltage (V th ) is −3.3 V and −1.9 V for the conventional mesa and fin-isolated HFETs, respectively. The less negative threshold voltage of the fin-type HFET compared to the conventional mesa device determines that a better electrostatic control is offered over the intrinsic gated channel of HFETs realized on narrower isolation feature which is mainly due to the triple-gate effect [18], peel force development (hence, strain minimization) [20], and the presence of surface states at the sidewall facets. Among which, the latter mechanism is believed to be the dominant mechanism for this positive shifting [21].

Results and discussion
Since the overall gate width is not identical among the two device categories, to perform a fair assessment of the gate-leakage we have calculated the scaled-up gate current of a fin-type HFET consisting of 110 fins, yielding the  same width as the fabricated conventional mesa HFET. As shown in figure 3, at all values of V GS the gate current of the fin-type HFET with the same overall gate width as the conventional mesa is more than one order of magnitude higher than that of the mesa counterpart.
Although in the fin-type category a larger area of the gate finger is in contact with the etched GaN surfaces, for the measurements performed at zero drain-source voltage, based on reported observations only leakage via the sidewall contact to 2DEG seems viable [13]. Therefore, observations made in figure 3 suggest that compared to the mesa-type HFET, in devices comprising of much smaller fin widths, and consequently larger number of sidewalls to yield the same overall gate width as a single mesa, sidewall leakage could be prominent in determining the gate-leakage even at V GS values below the threshold voltage.
In order to substantiate this speculation, the amount of leakage due to each of the assumed individual leakage components (i.e. leakage to the 2DEG through the gated sidewalls and through the top surface gate) should be separately identified. Relying on the prior evidence [4,10,14] to this end we have modeled the gateleakage speculating FN as the mechanism responsible for the leakage through the top-surface gate for more negative values of V GS . Accordingly, the current associated with the FN process is calculated by [5], in which q is fundamental electronic charge, h is the Planck's constant, m e is the free electron mass, m n AlGaN , * is the conduction band effective electron mass in the barrier layer, q b j is the Schottky barrier height considering the Schottky barrier lowering and As per [6], based on the information on the presence of inhomogeneity of the vertical electric field across the barrier of III-nitrides [6,9,22,23], the current due to the FN tunneling mechanism is position-dependent. Therefore, the FN-related current which leaks through a part of the barrier that boasts a higher electric field dominates the total leakage current through the barrier. This small portion of the barrier through which FN tunneling predominantly takes place is called the 'FN leakage-zone (S FN )' and the magnification of the electric field across this zone is defined by the γ factor. In our analysis in assessing the current associated with the FN process (I FN ) in terms of (1), E which is the electric field half way through the barrier under the gate is calculated employing COMSOL Multiphysics [24]. The accuracy of the calculated electric field using COMSOL is confirmed by its similar value calculated by (3) [4] in which qΔj c is the conduction-band discontinuity at the barrier/channel hetero-interface, qj F is the difference between fermi energy level and conduction-band edge at the GaN side and d barrier is the barrier thickness. Device parameters used in COMSOL simulations are summarized in table 1 [25].  Figure 4 demonstrates the profile of the vertical electric field in the middle of the barrier along the channel of AlGaN/GaN HFETs of two different isolation feature geometries having similar electrical characteristics such as V th with the fabricated HFETs. As demonstrated in this figure, the strength of the vertical electric field is almost constant under the gate for V GS values above the threshold voltage, while it is larger at the gate edges for V GS values below the threshold voltage. Therefore, for calculating I FN we have integrated the current due to the FN process at each mesh point in COMSOL simulations over the length of the gate. As an example, based on figure 5, the vertical electric field almost saturates at V GS values below the threshold voltage, which is due to the partial depletion of the 2DEG for this bias range. Due to the less negative threshold voltage of the HFET comprising of narrower fins, the saturation of the electric field occurs at a less negative V GS compared to the HFET of wider isolation feature. This is why below V GS of −1.9 V (i.e. the threshold voltage of the narrower fin HFET) the vertical electric field is stronger in the HFET of wider isolation feature.
Based on (1), the V GS range across which I FN takes the dominant role is where a linear dependence of Ln(I G /(γE) 2 ) versus 1/γE is observed. In establishing this trend, the value of γ was initially adopted from [6], and was gradually increased until the slope of Ln(I G /(γE) 2 ) versus 1/γE is proportional to m . n b 3 j * Accordingly, as shown in figure 6 the intercept of Ln(I G /(γE) 2 ) versus 1/γE curve with the vertical axis determines the value of S . FN Further below, it is shown that the calculated values of S FN and γ provide the best match between the measured gate current and modeled I FN at more negative values of V GS in the mesa isolated HFET.
It is worth mentioning that the absence of such a linear relationship in the Ln(I G /(γE) 2 ) versus 1/γE characteristics of the fin-isolated HFETs indicates the lack of the dominance of FN for any value of V GS in this device type. Furthermore, we have assessed the suitability of other vertical leakage mechanisms such as PF, TAT and phonon-assisted tunneling (PhAT) [26] in predicting the observed leakage trend in the fin-type HFETs. However, these trap-related mechanisms also fall short in acceptably modeling the gate-leakage in these HFETs. Based on this observation and our earlier speculation on the dominance of leakage through the gated sidewalls in HFETs realized on fins across the whole range of the explored V GS , we have investigated the applicability of TAT and PF to this leakage path. However, due to the depletion of the 2DEG below the threshold voltage PF is incompetent in predicting the gate-leakage for this bias range. PhAT also is more dominant at higher temperatures and V DS values [27]. This is while the TAT mechanism taking place between the gated sidewalls and the 2DEG of the explored fin-type HFETs provides sufficient evidence on the dominance of this mechanism not only for V GS >V th but also for V GS <V th . Accordingly, sidewall leakage due to TAT is calculated using (4) [4] in which S Sidewall is the area of the gated sidewall through which leakage occurs, E Sidewall is the electric field defined in terms of the potential difference between the gate and the 2DEG calculated employing COMSOL (figure 7), and P 1 and P 2 represent probability of the tunneling process from metal to the lower edge of the localized trap band and from the higher edge of the trap band to 2-DEG, respectively and N t is the trap concentration. Table 2 presents the values of the parameters used in calculation of the currents associated with each leakage mechanism.
Using (1) and (4) as shown in figure 8, within the range of 0 V to −4 V of the V GS in the fin-type HFET the dominant leakage mechanism is TAT through the gated sidewalls. However, as demonstrated in figure 9, in the mesa HFET FN process through the top surface gate is the dominant leakage mechanism for gate voltages below −3 V and TAT through the gated sidewalls is dominant for V GS >−3 V. It is worth mentioning that V GS of −3 V is the same voltage where a kink in the measured gate current versus V GS curve is observed in mesa-type HFET (solid curve in figure 9). In other words, the sudden increase in the saturated gate current at V GS = −3 V is because at this point vertical leakage due to the FN process which exponentially increases with the electric field prevails the sidewall leakage due to TAT. This is while in the fin-type HFETs the dominant leakage path is through the gated sidewalls at all values of V GS . This dissimilarity in the dominance of the gate-leakage mechanism at V GS <V th among the explored mesa and fin-type HFETs is attributed to the difference in the  profile of the electric field among these device categories for large negative values of V GS . In broad terms, the vertical electric field, which exponentially impacts the vertical leakage due to FN process almost saturates for V GS <V th . Therefore, compared to the conventional mesa the electric field of the fin-type HFET saturates earlier due to its 2 orders of magnitude smaller gate width and consequently less negative value of V th . Accordingly, even at large negative values of V GS the leakage due to the FN process is smaller in the fin-type HFET compared to the mesa category.

Conclusion
Reverse gate-leakage at V DS = 0 V is investigated over AlGaN/GaN HFETs realized on fins and mesa-isolation features and it is shown that two main leakage mechanisms that contribute to the total gate-leakage at room temperature are FN and TAT. It is demonstrated that due to the positive shift of threshold voltage in devices realized on fins of smaller widths compared to the wider mesas, the saturation of their electric field across the barrier happens at a less negative value of V GS . Accordingly, at any value of V GS below the threshold voltage of the fin-isolated HFET, the electric field across the barrier of the mesa HFET is stronger, which results in its exponentially larger value of the FN-related leakage component compared to the fin counterpart. While it is demonstrated that in the leakage characteristics of the mesa HFET there is a turning point below which FN Figure 8. Log-scale gate current components of an HFET with a 400 nm-wide fin, the dotted curve is the leakage due to the TAT process through the gated sidewalls, the dashed curve is the leakage current due to the FN process through the top surface gate and the solid curve is the experimentally measured leakage current of this HFET. Figure 9. Log-scale gate current components of an HFET realized on a 44 μm-wide mesa, dotted curve is the leakage due to the TAT process, the dashed curve is the leakage current due to the FN process and the solid curve is the experimentally measured leakage current of this HFET.
process takes the dominant role, in the fin-type HFET, even at the extreme negative end of the explored gate voltages, sidewall leakage due to TAT is superior to the vertical leakage due to the FN process. Although leakage due to the FN process is substantially larger in the mesa HFET, the total amount of gate-leakage is higher in the fin type HFET consisting 110 fins to yield the same overall gate width as the conventional mesa. This indicates the importance of sidewall leakage in devices comprising of a large number of fins of sub micrometer width. Consequently, devices made on narrow fins while offering a luring avenue for V th tuning and realization of enhancement-mode devices, need to pay an excessive price in terms of reverse gate-leakage current, unless suitable solutions such as properly isolating the sidewalls are considered.