Reﬂectometry of charge transitions in a silicon quadruple dot

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I. INTRODUCTION
Spin-based quantum computing based on silicon quantum dots is rapidly evolving [1], motivated in part by the prospect of scalable foundry fabrication that so far allowed coherent control of hole spins [2,3] and electricallydriven electron spin resonance [4]. Foundry-fabricated nanowire devices controlled by split-pair side gates recently allowed various spin-relaxation experiments [5,6] and charge-sensing functionalities [7][8][9][10]. However, scaling from few-qubit circuits towards fault-tolerant quantum processors will likely involve dense two-dimensional arrays of singly-occupied quantum dots [11,12].
To date, all semiconducting 2x2 arrays operated in the one-electron regime relied on proximal sensors to establish the number of electrons in the array [13][14][15][16][17]. In this article, we focus on gate-based reflectometry of charge transitions in a two-dimensional silicon quadruple dot, demonstrating charge sensing, dispersive readout, and single-electron occupation of all four quantum dots. Measurements are supported by a constant interaction model that captures multi-dot Coulomb blockade and a k · p model that confirms a dependence of tunnel barriers on a global top-gate voltage. Finally, we study the dependence of characteristic tunnel times on dot detuning and demonstrate single-shot detection of interdot charge transitions at larger bandwidths than state-of-art.
Section II introduces the device and pulsed-gate reflectometry setup. Section III establishes the tunability of interdot tunnel rates by application of a top-gate voltage, * kuemmeth@nbi.dk † These authors contributed equally to this work.
supporting k · p modeling by experimental data. Section IV explains how reflectometry off one gate electrode allows detection of the first electrons on all four quantum dots. Section V introduces compensated control voltages for acquiring multi-dot charge stability diagrams via radio-frequency reflectometry. Section VI reports the dependence of characteristic tunnel times on dot detunings and single-shot readout traces in time domain. Figure 1a shows the device chip wirebonded to a highfrequency printed-circuit-board chip carrier that also provides reflectometry functionalities via a surface-mounted inductor L, a coupling capacitor C C , and a bias resistor R B . An undoped silicon nanowire of width W = 70 nm and thickness t Si = 7 nm is connected to highly-doped source and drain contacts (Fig. 1b). Four accumulation gate electrodes G 1−4 induce electrostatically-defined quantum dots (QDs) under each gate for sufficiently positive gate voltages [7]. Gate lengths L G =32 nm and vertical and horizontal spacings S V =S H =32 nm are defined by hybrid deep-ultraviolet and electron-beam lithography and silicon-nitride spacers [19,20]. The gate stack comprises a 6-nm SiO 2 gate dielectric capped by 5-nm TiN and 50-nm doped polycrystalline silicon, as shown in Fig. 1c for a similar device. Figure 1d summarizes the wiring between room temperature electronics and the device located inside a cryofree dilution refrigerator. The sample holder at 0.05 K allows measurements of source-drain current (I, measured via thermalizing filters [18]) and radio-frequency measurements via port 1 (RF IN ) and port 2 (RF OUT ), building on earlier gate-based reflectometry [21].   A SG383 vector source generates a reflectometry carrier that is attenuated and phase-shifted at room temperature and further attenuated inside the cryostat (36 dB distributed between 50, 4, and 1 K) before passing a directional coupler (MC ZFDC-20-5-S). The signal reflected from the LC resonator is amplified at 4 K (35 dB, Weinreb CITLF1) and further processed at room temperature for demodulation, amplification, low-pass filtering (SR560) and digitization (AlazarTech ATS9360). Here, L=820 nH is a surface-mounted copper inductor (Coilcraft 1206CS-821XJL) and C constitutes a parasitic capacitance to ground associated with bond wires and metal tracks (not shown in Fig. 1d, estimated 0.85 pF from the observed resonance at 191 MHz). The 191-MHz carrier (-75 dBm incident on L) results in a demodulated background amplitude of 0.2 V. By adjusting the phase shifter, the demodulated quadrature V H is reduced to approximately 0 and then changes by typically 0.01 V when the sensor dot is active, corresponding to a change in the phase of the reflected carrier of approximately 2 • .

II. DEVICE AND SETUP
Side gates G 1,2,3 are wirebonded to bias-tees so that low-frequency tuning voltages and high-frequency control pulses can be applied simultaneously. The highbandwidth sample holder is available for multi-channel quantum electronics experiments [18] and features highfrequency grounds (SMD capacitors to ground) on all Vtg (V) 300 nm 220 nm low-frequency channels, including source and drain wires. For fast voltages pulses V F 1,2,3 (t), coaxial cables are attenuated by 28 dB distributed between 50, 4, 1 and 0.05 K. Low-frequency (high-frequency) control voltages are generated by a high-resolution QDAC [18] (Tektronix AWG5014C), and no external magnetic field is applied.
Despite the small number of gate electrodes, tunnel rates can be adjusted in situ via a 200-nm-long copper electrode (top gate) that runs across the device center 300 nm above the nanowire (Fig. 2a). Its wiring is identical to that of the low-pass-filtered source and drain wiring (not shown in Fig. 1d). Alternative barrier tuning via a highly-doped silicon layer below the buried oxide (BOX) was demonstrated in Ref. 22 for similar nanowire devices.

III. TUNABILITY OF QUADRUPLE DOT BY TOP GATE: MODELING AND EXPERIMENT
We now demonstrate theoretically and experimentally the global tunability of the tunneling rates between dots via the top gate. Informed by the measured device, our k · p model considers an accurately-sized nanowire together with its surroundings: source and drain reservoirs, gate electrodes, gate spacers and BOX substrate (see Fig. 2a and appendix A for details). After selfconsistently solving the potential in the device in the Thomas-Fermi approximation, the energies and wave functions of the tunnel-coupled single-electron quantum dots are computed with an anisotropic effective mass method. Figure 2b shows the longitudinal t || , transverse 20 t ⊥ , and diagonal t d tunnel couplings as a function of top-gate voltage, with wavefunctions visualized in panels c-e. While t ⊥ and t d strongly depend on V tg , t || shows a weaker dependence likely due to the short spacer S H and the larger local screening arising from the geometry of adjacent wrap-around gate electrodes. Interestingly, t ⊥ is small at low top-gate voltages, becomes comparable to t || at V tg ≈5 V and is an order of magnitude larger at V tg =20 V, suggesting the use of global top gates to tune the ratio of transverse and longitudinal couplings (t ⊥ /t || ). Independent simulations in Ref. 9 for similar devices also found a significant effect of the top gate.
Our simulations also indicate large charging energies associated with each QD (17 meV) and large gatecoupling strengths (0.6 eV/V at V tg =0), which is attractive for high-temperature operation, dispersive gate sensing with high signal-to-noise ratios, and strong coupling to resonators or microwave cavities.
Experimentally, measurements of Coulomb diamonds as in Fig. 3a reveal charging energies of 15-20 meV and gate strenghts of 0.4-0.5 eV/V for all four QDs, consistent with simulations. The tunability of tunnel rates by the top gate is evident by a change of current when the device is biased as a serial double dot: Figure 3b shows an increase in I when the same bias triangles are measured at V tg =6 V, and a 100-125 mV shift of these bias triangles towards lower values of V 1 and V 4 , consistent with a capacitive coupling of the top gate to dot potentials measured independently. Alternatively, characteristic tunnel times for different top-gate voltages can be measured in time domain using high-bandwidth reflec-  tometry (section VI), as recently reported in Ref. [7].

IV. SINGLE-ELECTRON OCCUPATIONS
For the remainder of this article, source and drain contacts are grounded for reflectometry measurements. To achieve high-visibility Coulomb oscillations in V H (V 4 ), QD 4 is first configured in the multi-electron regime (9-12 electrons). Non-participating dots remain empty by applying 0 V to their gates. Multi-electron occupation increases the coupling strength of the LC resonator to QD 4 and the tunnel rate between QD 4 and its reservoir, thereby facilitating dispersive sensing [23]. The large capacitive shift arising from the first and second electron on QD 1 (red dashed lines in Fig. 4a) is qualitatively consistent with the relatively large dot-to-dot capacitance inferred from triple-dot measurements in Fig. 5 (see capacitance values in appendix B).
The reflectometry signal does not reveal single-electron charging of QD 4 , likely due to its small tunnel rate relative to the reflectometry frequency (191 MHz) [23]. In Figure 4d, we therefore configure QD 3 in the multielectron regime, yielding sufficient tunnel coupling to its reservoir and sufficient capacitive coupling to the reflectometry gate G 4 to yield visible Coulomb oscillations in V H (V 3 ). In this way, discrete capacitive shifts of these Coulomb peaks indicate the first and second electron on QD 4 (black dashed lines). For this measurement, QD 1 and QD 2 were kept empty (V 1,2 =-0.2 V).

V. CHARGE STABILITY DIAGRAMS USING COMPENSATED CONTROL VOLTAGES
The sensitivity of Coulomb oscillations of QD 4 (from now on referred to as sensor dot) to nearby charge rearrangements can be further utilized by applying compensated control voltages, i.e. linear combinations of native gate voltages V 1,2,3,4 such that changes applied to compensated voltages do or do not change the chemical potential of the sensor dot. Such compensated control voltages are visualized in Fig. 4 as arrows. Experimentally, they are implemented by calibrating capacitive matrix elements α 4i such that V 4 compensates for electrostatic cross coupling between gates G 1−3 and QD 4 , i.e. by up- . The choice of positive (negative) values for α 4i is indicated by adding a superscript + (-) to the respective control voltage, with α 4i listed in appendix C. Using this compensation, and by setting the desired operating point of the sensor dot via V o 4 , the associated reflectometry signal V H becomes sensitive to charge rearrangements within the array.
Positive compensation is useful for acquiring large stability diagrams of QD 1 , QD 2 , and QD 3 , as it increases the density of Coulomb peaks associated with QD 4 and thereby facilitates the identification of charging events. (This can be seen by comparing the density of sensor peaks in Fig. 6a with that in Fig. 4.) Negative compensation, for accurate choices of V o i and α 4i , has an intuitive physical interpretation: sitting on a Coulomb peak, as long as the (enhanced) reflectometry signal is unchanged, there are no charge rearrangements within the quadruple dot except for a continual exchange of electrons between QD 4 and its reservoir. This allows the study of charge state boundaries, demonstrated below for a triple-dot configuration relevant, for instance, for the spatial permutation of isolated fermions [7] or the implementation of exchange-only qubits [24]. Figure 5a shows a capacitive circuit model for the charge occupation 3058, and its simulated ground-state region in gate-voltage space. (Here, the ith digit indicates the number of electrons on the ith dot.) This triple-dot constant interaction model is appropriate for sufficiently small tunnel couplings within the array [25]. Points representing the 3057-3058 ground-state degeneracy are shaded in yellow, indicating that a compensated scan of this region is expected to yield enhanced reflectometry signals arising from QD 4 . In contrast, a native cut at fixed V 4 is shaded in blue, indicating that a low reflectometry background is expected due to all groundstates in this region having a fixed charge on QD 4 . Using capacitance values inferred from measurements, simulations reveal that ground-state boundaries can appear hexagonal (as in the native plane of Fig. 5b) or tetragonal (as in the negatively compensated plane of Fig. 5c).
To verify this observation experimentally, we set V o i and α 4i appropriate for configuring the device in the 3058 occupation and initially acquire uncompensated Coulomb oscillations associated with QD 4 (Fig. 5d). Fixing V 4 inside the 8th Coulomb valley then yields uncompensated stability diagrams as in Fig. 5e. As expected, no Coulomb peaks of QD 4 are visible (note colorscale in Fig. 5d), but faint hexagonal features are clearly visible that correspond to smaller dispersive signals arising from charge transitions of QD 1 and QD 3 . In contrast, choosing an operating point on the 7th sensor peak yields negatively compensated charge stability diagrams as in Fig. 5f, dominated by a tetragonal region with a V H intensity consistent with the sensor peak indicated in Fig. 5d. Well-known for capacitively coupled triple dots [26], some charge state boundaries cannot be crossed by oneelectron transitions alone and require two single-electron movements or two-electron cotunneling events, such as transitions 2058-3067 and 3048-4057 in Fig. 5c. Surprisingly, these higher-order multi-electron dynamics clearly manifest themselves in the dispersive signal, at least for the high top-gate voltage used in Fig. 5f.
To show the practical differences between positive and negative compensation, we plot in Fig. 6b a negatively compensated charge stability map of a transverse double dot (i.e. QD 3 deactivated) and in Fig. 6a a positively compensated map containing the same charge states (in both cases, QD 4 is operated in the multi-electron regime to enhance V H ). The high density of sensor peaks in Fig. 6a makes it easy locate the degeneracy points associated with QD 1 and QD 2 (dashed lines), whereas the exact boundaries of individual charge states remain elusive. In contrast, Figure 6b yields the exact shape of a particular charge-state boundary, from which device capacitances analogous to Fig. 5a can be extracted.
The observation of a hexagonal region in Figure 6b, opposed to a tetragonal region as in Fig. 5f, indicates that the two array configurations are represented by triple-dot circuits that are qualitatively different in terms of their effective capacitances.
Compared to double dots with proximal charge sensors [21], which can also be viewed as triple dots, the relatively strong capacitive coupling between sensor dot , revealing a tetragonal region of enhanced reflectometry signal (QD4 transitions). Here, the superscripts indicate that V4 is negatively compensated when sweeping V1 and V3 (as illustrated in Fig. 4 a,c), thereby maintaining the 3057-3058 degeneracy of the sensor dot (as indicated in d) within the tetragonal region. Vtg=12 V and V2=0 V. Panels e and f use colorscale in d. Red and black numbers denote occupation of QD1,2,3 and QD4, respectively. and other dots in the 2x2 array also makes uncompensated charge stability diagrams qualitatively different, in the sense that only two or three charge states near a double-dot triple point can be distinguished. This is evident in Figure 6c, where certain charge transitions like 000-010 cannot be distinguished despite the use of an intentionally power-broadened sensor peak. This sensitivity is useful when only one charge transition needs to be detected, in which case its visibility can be optimized or even reversed by adjusting the sensor operating point. For example, raising V 4 by only 4 mV yields the opposite V H contrast for the same 100-010 transition (Fig. 6d).
Negative compensation suffers from a similar "strong coupling" problem, making it difficult to distinguish multiple charge states within one charge stability map. Between panels 6e and 6h, only V o 4 was adjusted, resulting in an enhancement of V H for four different charge states.
Recently, a different method to mitigate the strong capacitive coupling between dots achieved charge sensing by rastering native gate voltages and plotting the Coulomb-peak position of the sensor dot (quantified as a change in sensor-dot voltage) [27].

VI. TIME-RESOLVED SINGLE-ELECTRON DYNAMICS
The combination of fast voltage pulses V F i (t) and timeresolved digitization of V H (t) allows the temporal study of single-electron tunneling within the array and to reservoirs, exemplified in the inset of Fig. 7a by purple and orange arrows, respectively. The controlled loading of an electron from a reservoir to QD 2 is facilitated by first acquiring a charge stability map in the absence of voltage pulses (Fig. 7a), and then locating an operating point suitable for exchanging an electron with the reservoir by application of a periodic square wave (orange arrow). During such gate-voltage trajectories QD 1 and QD 3 are empty and remain in Coulomb blockade. In Figure 7b, we continuously apply a square wave with period 1.2 ms and amplitude 2 mV (inset, referred to G 2 taking into account attenuation in the cryostat) while slowly stepping V 2 across its operating point at 50 mV. For each value of V 2 , we acquire the average of 5000 single-shot traces, each acquired with a sample rate of 1 MS/s and a demodulation bandwidth of 1 MHz, which we then normalize [28] and plot as oneV H (τ M ) column. For V 2 =49-51 mV, the pulse trajectory is straddling the charging threshold of QD 2 , evident byV H (τ M ) decaying from 1 to 0. (For smaller or larger values of V 2 QD 2 remains empty or filled, as expected for a 2-mV pulse amplitude.) To extract characteristic tunnel times, we fit exponential decays toV H (τ M ) as shown in Fig. 7c (solid  lines). For clarity, only selected values of V 2 are shown, andV H (τ M ) has been decimated by a factor of 7 to reduce the number of markers. Figure 7d plots mean life times extracted in such manner as a function of detuning of the QD 2 potential. As the measurement point is moved from the degeneracy point deeper into the one-electron Coulomb valley, we observe an increase of tunnel times followed by a decrease. The maxima (green marker) of such data sets were utilized recently to quantify the effects of the top gate on tunneling times [7].
Lastly, we demonstrate single-shot detection for the example of an interdot transition between QD 2 and QD 3 .
An uncompensated charge stability diagram (Fig. 7e, inset) is used to define a three-step gate-voltage cycle that repeatedly crosses charging thresholds of QD 2 and QD 3 (to refresh electrons from the reservoir) as well as the interdot transition from QD 2 to QD 3 (purple arrows). Each cycle gives rise to one single-shot readout trace, sampled at 100 kS/s with a demodulation bandwidth of 30 kHz. Figure 7e shows 100 such traces for 20-mslong segments spent at the measurement point M, with stochastic charge transitions clearly visible by eye. Fitting a double Gaussian to the histogram of all pixels, we determine a signal-to-noise ratio of 1.4 for a 30-kHz bandwidth [29], ten times higher than in recent gatebased reflectometry readout in silicon nanowire, planar, and donor-based devices [30][31][32].

VII. CONCLUSIONS
This work demonstrates gate-based reflectometry measurements of various few-electron charge states in a twodimensional quadruple dot implemented by 300-mmwafer foundry fabrication. The strong mutual capacitances within the densely-packed (64-nm gate pitch) array of silicon quantum gots allows detection of singleelectron tunneling in all four dots using only a single LC resonator, wirebonded to one of the four side gates and monitored by radio-frequency reflectometry. Tunnel rates can be adjusted over several orders of magnitude by application of moderate top-gate voltages, while positive and negative compensation of the sensor dot potential yields convenient multi-dot stability diagrams with qualitatively distinct charge-state polytopes, as exemplified for a triple-dot configuration. Finally, we demonstrate a considerable improvement in the readout bandwidth for single-shot gate-based reflectometry in silicon devices.
Further improvements in bandwidth, signal-to-noise ratio, and scalability may be possible by the use of Josephson parametric amplifiers [33,34], better impedance matching [35], or integration with cryogenic control electronics [34,36]. Improved device geometries may harness individual control of tunnel barriers through advancements in three-dimensional verylarge-scale integrated-circuit (3D VLSI) fabrication technologies [37]. Leveraging large gate capacitances and electrically-driven electron spin resonance [4] may then spark diverse applications for foundry-fabricated devices in circuit quantum electrodynamics [10], quantum simulations, and spin-based quantum information processing.

VIII. ACKNOWLEDGEMENTS
We thank Silvano De Franceschi for the coordination of samples. This work received funding from EU grant agreements No. 951852, 688539, 676108, and 323841. H.B. and F.A. contributed equally to this work.

A. Details of the k · p modeling
The device used for k · p modeling comprises a silicon channel (W = 70 nm, t Si = 7 nm, L NW = 165 nm) with gate lengths L G = 32 nm and gate spacings S V = S H = 32 nm, consistent with the experimental device. The simulated gate stack comprises 6 nm of SiO 2 , 5 nm of TiN and 45 nm of poly-Si. Gates are capped by 25 nm of Si 3 N 4 from each side, to model similar caps in the measured device that prevent dopants (implanted via ion implantation during source/drain doping) to penetrate into the channel. The whole device is encapsulated in SiO 2 , with the 200-nm long top gate running 300 nm above the channel.
To capture electrostatic effects arising from the reservoirs, 20-nm raised source and drain contacts have been added to both ends of the channel. They are highly ndoped (N d = 10 20 cm −3 ). Along the channel, the density of donors decreases by one order of magnitude every 4 nm starting at the outer edges of the source/drain spacers. Therefore, the regions underneath the gates and underneath the central spacers are practically undoped. The poly-Si gate is also n-doped (N d = 2 × 10 19 cm −3 ), while the silicon substrate below the 145-nm thick BOX layer is slightly p-doped (N a = 10 15 cm −3 ). We account for a 0.25 eV Schottky barrier at the interface between the poly-Si and TiN gates, informed by threshold voltage shifts measured at room temperature in similar devices with polysilicon-only gates. The dielectric constants of the materials are Si = 11.7, SiO2 = 3.9, and Si3N4 = 7.5. TiN is modeled as a perfect metal.
Traps have been added at the SiO 2 /Si 3 N 4 interface in order to account for charge disorder in the amorphous materials. These traps are modeled as a continuous distribution of charges with areal density σ = −5 × 10 11 e·cm −2 . They decrease the overall magnitude of the tunneling rates, yet have no impact on their tunability with respect to the top gate.
The potential in the device is computed selfconsistently within the Thomas-Fermi approximation. For numerical convenience, we assume a temperature T = 4.2 K and account for incomplete ionization of the dopants at this temperature [38]. The one-particle states in the ground-state Z valley are calculated with a finite differences implementation of the anisotropic effective mass approximation [39].
We sweep the top-gate potential with the source, drain, and back-gate grounded. We apply the same voltage on all side gates G 1 -G 4 such that the ground-state energy of the four-dot system remains resonant with the chemical potential of the source and drain. We then map the energies and wave functions of the four lowest-lying states onto the following effective Hamiltonian: where E Qi are the energies of the isolated QDs, t || is the tunnel coupling between neighbouring QDs along the channel, t ⊥ is the tunnel coupling between opposite face-to-face QDs, and t d is the tunnel coupling between diagonal QDs. With the same voltage on gates G1-G4, the system remains at a degeneracy point where E Q1 = E Q2 = E Q3 = E Q4 = E 0 . The eigenenergies and parity (sign) of the wave functions in each dot are therefore: Once the calculated states have been unambiguously identified by their parities, t || , t ⊥ , and t d can be fitted to their energies using the above equations.

B. Details of the constant-interaction capacitance model for the triple-dot configuration
To simulate Figure 5b,c from the main text, we assume that the electrostatics of the triple-dot configuration can be described by a constant interaction model [25] that is represented in Figure 5a as a circuit of 12 capacitors. For sufficiently small tunnel couplings, this approximation is expected to be sufficient to capture the ground-state geometry (in gate-voltage space) of a charge configuration. Since QD 2 was not activated in the experiment by setting V 2 to 0 V, we use in Figure 5a a capacitance circuit that only involves QD 1 , QD 3 , and QD 4 . (In reality, geometric capacitances associated with QD 2 and G 2 will contribute to some of these effective circuit capacitances.) To simulate the Coulomb valley of the 3058 configuration, we use the following capacitance matrix informed from experimental stability diagrams: where diagonal elements C ii correspond to the capacitive coupling between gate G i and dot QD i , and off-diagonal elements C ij correspond to the capacitive coupling between gate G j and dot QD i . All capacitances are given in units of aF. In addition, the following dot-to-dot capacitances were used for the simulations in Figure 5b and 5c: QD 1 -to-QD 3 =0.25 aF, QD 1 -to-QD 4 =1.25 aF, QD 3 -to-QD 4 =0.75 aF. As indicated in Figure 5a, the smallest capacitance in the circuit is the "diagonal" capacitance between QD 1 and gate G 3 (0.25 aF), whereas the largest capacitance is the capacitance between QD 4 and gate G 4 (5.5 aF), consistant with its high occupation number.