Pseudo-2D superconducting quantum computing circuit for the surface code

Of the many potential hardware platforms, superconducting quantum circuits have become the leading contender for constructing a scalable quantum computing system. All current architecture designs necessitate a 2D arrangement of superconducting qubits with nearest neighbour interactions, compatible with powerful quantum error correction using the surface code. A major hurdle for scalability in superconducting systems is the so called wiring problem, where qubits internal to a chip-set become inaccessible for external control/readout lines. Current approaches resort to intricate and exotic 3D wiring and packaging technology which is a significant engineering challenge to realize, while maintaining qubit fidelity. Here we solve this problem and present a modified superconducting scalable micro-architecture that does not require any 3D external line technology and reverts back to a completely planar design. This is enabled by a new pseudo-2D resonator network that provides inter-qubit connections via airbridges. We carried out experiments to examine the feasibility of the newly introduced airbridge component. The measured quality factor of these new inter-qubit resonators is sufficient for high fidelity gates, below the threshold for the surface code, with negligible measured cross-talk. The resulting physical separation of the external wirings and the inter-qubit connections on-chip should reduce cross-talk and decoherence as the chip-set increases in size. This result demonstrates that a large-scale, fully error corrected quantum computer can be constructed by monolithic integration technologies without additional overhead and without special packaging know-hows.

Of the many potential hardware platforms, superconducting quantum circuits have become the leading contender for constructing a scalable quantum computing system. All current architecture designs necessitate a 2D arrangement of superconducting qubits with nearest neighbour interactions, compatible with powerful quantum error correction using the surface code. A major hurdle for scalability in superconducting systems is the so called wiring problem, where qubits internal to a chip-set become inaccessible for external control/readout lines. Current approaches resort to intricate and exotic 3D wiring and packaging technology which is a significant engineering challenge to realize, while maintaining qubit fidelity. Here we solve this problem and present a modified superconducting micro-architecture that does not require any 3D external line technology and reverts back to a completely planar design. This is enabled by a new pseudo-2D resonator network that provides inter-qubit connections via airbridges. We carried out experiments to examine the feasibility of the newly introduced airbridge component. The measured quality factor of these new interqubit resonators is sufficient for high fidelity gates, below the threshold for the surface code, with negligible measured cross-talk. The resulting physical separation of the external wirings and the inter-qubit connections on-chip should reduce cross-talk and decoherence as the chip-set increases in size. This result demonstrates that a largescale, fully error corrected quantum computer can be constructed by monolithic integration technologies without additional overhead and without special packaging knowhows.
Recently, architecture designs for large-scale quantum computers are becoming more and more comprehensive. This field frequently includes a large amount of quantum engineering specifying how qubits will be manufactured, controlled, characterized and packaged in a modular manner for faulttolerant, error corrected quantum computation [1][2][3][4][5]. The vast majority of architectures base their designs on the surface code because it has one of the highest fault-tolerant thresholds of any error correction code, easing the physical fidelity requirements on the hardware.
Superconducting quantum circuits have emerged as a major contender for a scalable hardware model for the surface code. Superconducting qubits are fabricated with inter-qubit wirings for nearest neighbor interactions and each individual * e-mail: tsai@riken.jp qubit requires external physical access such as bias lines, control lines, and measurement devices. However, as the 2D array is scaled up, planar accessibility for control lines become a problem. Such challenges are sometime referred to as the wiring problem, where physical qubits in the interior are no longer accessible, in plane, from the edge [6].
Compared with classical silicon integrated circuits, it is much more difficult to achieve such wiring in superconducting quantum circuits. To individually access every qubit in the 2D qubit array, standard multi-layer wiring technologies for silicon integrated circuits simply cannot be embraced as it generally requires the introduction of decoherence enhancing, low quality inter-layer insulators. Therefore, in current superconducting systems, many groups are forced to utilize non-monolithic bulky 3D wiring technologies (see Fig. 1), such as flip-chip bonding, Pogo pin and through silicon via (TSV) [7][8][9][10][11][12][13][14].
Our new architecture for the surface code is obtained by transforming the 2D qubit array to a bi-linear array. Fig. 1 shows the mapping between before and after the transformation. The square lattice Fig. 1(a) is divided into many columns. Next, the connections between columns are stretched [ Fig. 1(b)], and then, the columns are folded on top of each other successively, as shown in Fig. 1(c). The resulted equivalent surface code circuit is a bi-linear array of the original 2D structure.
The folding operations liberate the columns locked deeply inside the original 2D lattice and brings them out to the edges of the bi-linear array. Therefore the external control/readout lines connected to each qubit are accessible from the edges of the chip. This novel arrangement allows all these external connection to be prepared in a completely standard 2D layout.
The advantage gained in the external wiring by the transformation, however, takes a small toll in the inter-qubit wiring between columns. These inter-qubit connections between neighboring columns require multi-level crossings. Nonetheless, these 3D structures only need to locally hop over interqubit connection lines. Thus, the cross-connections between the columns can be described as pseudo-2D.
In comparison, for the original surface code architecture, the multi-layer wiring grid involves an inter-qubit connection layer and an input/output wiring layer. Therefore, a global multi-layer structure, as shown in Fig. 1(a), is often adopted, utilizing non-monolithic bulky 3D wiring technologies as mentioned earlier. Compared to the standard surface code arrangement, the new architecture has the following obvious advantages: between external lines and qubits. Undesired decoherence of qubits would also be prevented.
(2) 2D planar layout of the input/output wirings. These wirings, connecting qubits to external electronics and can be constructed by utilizing the standard 2D wideband (microwave) wiring technology. Superconducting resonators for the readout of the qubit can also be prepared with the standard 2D co-planar design.
(3) Local 3D (psuedo 2D) wiring. The ends of the interqubit connection lines always end up on the same qubit layer, no matter how many 3D hops are involved in the connection. In such case, the multi-layer crossing for the new architecture could be realized simply by local monolithic 3D structures, such as superconducting airbridges.
Moreover, the original square lattice architecture could adopt the local 3D structure (airbriges) for the wire crossings between input/output and inter-qubit connections. However, compared with the new architecture, such arrangement would produce strong cross-talk between external wirings and interqubit connection lines (cf. point (1) above).
Consequently, this architecture straightforwardly solves the demanding 3D external wiring problem. As already mentioned, a convenient technology to realize the cross wiring is an airbridge; a monolithic microstructure, developed as a lowloss wiring for superconducting qubits that can be fabricated in several ways, including a well-established standard fabrication process [15,16]. A large number of airbridges, compared with the number additionally required for this proposal, are always needed to maintain the uniform ground potential for all co-planar waveguide-based architectures.
To scale up the degree of integration, one needs to consider that increasing the number of qubits M in a column, which is represented as green, blue and red columns in a scaled-up structure of our proposed architecture [ Fig. 2(a)], would result with longer inter-qubit connection lines with more airbridges. Therefore, one should limit M to a minimally required number for a surface code based computer in effective 2D array. This is the arrangement before the transformation shown in Fig. 2(d)]. This limitation posed by the number of airbridges results in a subtle change in the design, compared with the standard 2D array for a surface code architecture.
Typical logical structure of the computer shown in Fig. 2 is a 2D array of qubits used for surface code computing, utilizing braid based logic [17]. Logical information is introduced by strategically switching on/off parts of the array to create and manipulate defects, which encode the logical qubits within the computer. The larger the 2D array at the physical layer, the more defects can be introduced for number of logically encoded qubits in the computer or the larger each defect can be for the strength of the error correction. Logic operations are then performed by topological braiding of the defects around each other. In Fig. 2(b), we illustrate a lattice that encodes two logical qubits via four pairs of defects introduced into the lattice (shaded regions), where two pairs are for each logical qubit. The defects are encoded using a d = 3 surface code, which can correct for an arbitrary single qubit error on either of the two encoded defect based qubits. In Fig. 2(c), we illustrate an encoded CNOT gate using braided logic [18]. Over time, the defects are moved throughout the lattice to enact topological braids, and the circuit is represented via a geometric diagram. The cross-section of the geometric representation of the circuit corresponds to the number of physical qubits required and the third dimension represents the logical computational time. In order to realize this defectbase structure, without significantly compromising the ability to efficiently enact arbitrary error-corrected circuits, requires the ability to arbitrarily scale in 2-dimensions. In our new design, however, the length of columns in the effective 2D array is limited -due to the number of airbridged crossings in a inter-qubit connection -but an arbitrary number of columns is allowed. Therefore, we envisage that lattice surgery encoded logic will be used instead of braid based logic [19]. In lattice surgery, isolated square patches of the planar code (single logical qubit, which is a surface code analogue that can encode a single piece of logical information) are interacted along a boundary to enact multi-qubit logic gates. This reduces the overall physical resource cost of each logical qubit and several results now suggest that lattice surgery techniques will always be more resource efficient when implementing large-scale algorithms [20][21][22].
For a single logical qubit encoded with the planar code, a square 2D array of physical qubits is needed. For a quantum code with a distance d, a (2d − 1) × (2d − 1) array of physical qubits is sufficient, the number of which can be reduced further utilizing rotated planar lattices [19,21] (but we omit this here for clarity). A illustrated layout is in Fig. 2(d). This results in a Linear Nearest Neighbour (LNN) logical layout of encoded qubits, requiring less physical resources than defect based logical qubits. In Fig. 2(d), you can see that there is additional columns of physical qubits only (red colors) that are spacers between each encoded qubit that is required to perform the lattice surgery operations. These advantages of the planar code are good compatibility for our architecture.
It should be noted that the current methods for circuit compilation using lattice surgery still assumes a 2D nearest neighbor arrangement of logically encoded qubits [20][21][22]. This is because lattice surgery has two basis classes of operations (merges and splits) over two types of boundaries for each planar code qubit (what are known as rough and smooth). As merge and split operations can only occur on the single bound-ary between logical qubit regions, we need to be able to convert between smooth and rough boundaries (which was detailed in Ref. [19]) and hence compilation into this LNN logical structure using pseudo-2D physical qubits layout will require some slight modifications over current techniques [20]. However, recent results that introduce a single additional row of physical qubits to act as a data bus for logic operations can be used and is completely compatible with a LNN arrangement of qubits at the logical level [23].
For a large error-correcting code, distance d can be of the order of d = 15 − 21 (capable of correcting up to 7-10 errors per logical qubit). With a distance d code requiring an array containing M = 2d − 1 rows of qubits with M = 2d − 1 columns, per single logically encoded qubit. Consequently, for a quantum computer containing N logical qubits on the planar code, we would utilize an array of M ×[N M +(N −1)].
Here, first M is the number of qubits in a column, and N M is the number of columns in the array for N logical qubits and the extra factor of (N − 1) is the spacing region between each logical qubit needed for the lattice surgery (or a bus system [23]). This would translate into a bi-linear array, as shown in Fig. 2(a) of 2 × 1 2 (2d − 1)(2dN − 1). A number of crossing points by inter-connections are at most half the number of qubits in a column, at most (2d − 1)/2 , representing the number of airbridges per resonator. The factor of 1/2 comes about due to the fact that alternate resonators (inter-connections) are shared by two qubits. Hence, while the number of columns N M linearly increases with the number of logical qubits, the number of airbridges contained in resonator will only be half number of qubits in a column (which is fixed for a given code distance, d).
In practice, the width of this array is related to the number of logical qubits while its length is given by the distance of the planar code used to encode each logical qubit. For a heavily error corrected logical qubit, d = 15-21, the total number of qubits in a column will be M = 29-41 with a maximum number of airbridges for a given resonator of 15-20. By utilizing planar code encoding and lattice surgery [19] for fault-tolerant logic, we can define our computer as a long, rectangular structure consisting of a Linear Nearest Neighbor (LNN) array of logical qubits (requiring compilation of the high level quantum algorithm with LNN constraints [20,23,24]).
To make a preliminary evaluation of this new architecture, we show the dependence of the fidelity on the quality factor of a resonator, of which the center line is composed of airbridges. Examining if airbridges can be used while still satisfying the error requirements for surface code quantum error correction, we carried out both experimental and numerical tests on a system containing a lossy resonator for connecting two qubits. Usual research in superconducting quantum circuit employ a very lossless resonator to eliminate its contribution. However there is little research related the dependence on the resonator quality factor. Therefore, the numerical test reveals a lower limit of the internal quality factor, and the experimental test illustrates the possibility that this proposed architecture is expected to be viable using current technology, without special 3D techniques.
We prepared chips using a standard fabrication method for including the interval of airbridge position is identical and fabrication conditions for each chip is also identical. Any difference in fabrication is only related to the number of airbridge (15 and 20). Each wafer were treated under the same conditions, but they were not fabricated at the same time. Fig. 3(a) shows the measured internal quality factor Q i of resonators containing 15 and 20 airbridges in the center conducting lines ( Fig. 3(b)), with reference resonators also illustrated. The quality factor of the resonator with airbridges at the center line, are > 2.3 × 10 4 at the power of the single photon level. In comparison with the reference co-planar resonators, which does not have airbridges, the quality factor decreased by about one order of magnitude. The quality factor of resonator with 20 airbridges is higher than one with 15 airbridges. The result of this reversal between 15 and 20 may be due to deviations that occur in the fabrication process.
To appraise the effect of extra loss resulting from the insertion of airbridges, we simulated an average gate infidelity of a CZ gate in our system, where two qubits are coupled through a damped (lossy) resonator. Here each qubit has three energy levels, anharmonicity η i , and the resonator has five energy levels with photon leakage rate (κ i = ω r /Q i ). We adjusted the state of the system to the condition for CZ gate which is that the energy difference from ground to first levels on one qubit is the same as the energy difference from first to second levels on the other qubit. Then, we calculated the time evolution of this system, and finally got the average gate fidelity F . Fig. 4 is the result of the simulation, showing the infidelity dependence on the quality factor of the resonator Q i . The result indicates that the required Q i for the infidelity threshold of the surface code (1 − F < 0.75 %) is 2 × 10 3 , and the infidelity is saturated at Q i > 10 4 .
The experimental internal quality factor of a resonator with airbridges at centerline one order of magnitude greater than what is required by our simulationse. In this experiment, current existing technologies were used. Therefore, this results strongly suggests that our proposed system, with real parameters, is feasible. The cross-talk between two crossing resonator lines is also evaluated with a network shown in Fig. 4(a). A feed line crosses two resonators, vertically, using an airbridge ( Fig.  4(b)). We measured the coupling strength between the feed line and resonators due to the airbridge structure. A reference continuous wave signal was applied through the feed line and the signals were absorbed at resonant frequency of the airbridge resonators, coming out with a small dip. The result showed the signal leakage to other lines due to the crossing airbridge was about 35 dB smaller than the through signal.
To conclude, we proposed the novel scalable architecture of a superconducting quantum circuit for the surface codes, where the standard planar 2D wirings can be adopted for external wirings, with the help of an airbridge-incorporated inter-qubit pseudo-2D resonator network. We also carried out the feasibility experimental study of the pseudo-2D resonator network, and showed that there is no fundamental difficulties in realizing it. Our result illustrates that a fault-tolerant, large-scale quantum computer could be constructed by simple monolithic integration technologies. Corresponding author: Correspondence and requests for materials should be addressed to J.S.T.

I. METHODS
Information on the simulation: We modeled a part of our system as two qubits coupled via a damped resonator, so the Hamiltonian is and this indirect-interaction of qubits (last term) is used for the CZ gate. The quantum map E can be derived solving the Lindblad master equation, and then we calculate the average gate (in)fidelity in computational subspace |ψ s between the map E and an ideal CZ gate map E CZ , which is defined as [26], averaged over the Haar measure dψ s . This simulation is performed using Quantum Toolbox in Python (QuTiP) [27]. Data availability: The data that support the findings of this study are available from the authors on reasonable request, see author contributions for specific data sets.