GaN-based cryogenic temperature power electronics for superconducting motors in cryo-electric aircraft

Climate change has spurred a shift to electric transportation, but aviation faces challenges with electric energy storage and propulsion. Cryogenically cooled superconducting motors, along with cryogenically cooled power electronics, offer a solution to increase the efficiency and power density of electric aircraft. This paper evaluates the feasibility of cryogenic power electronics by characterising new technologies (GaN, nanocrystalline) using new experimental techniques. It is found that the on resistance reductions of GaN E-high electron mobility transistors at cryogenic temperatures depend on the maximum blocking voltage of the device, and the size of the gate resistor for ohmic p-GaN devices. Different types of nanocrystalline cores are shown to vary greatly in their behaviour at cryogenic temperatures, which is measured using a modified core loss measurement circuit. Further analysis shows that the losses of a GaN based cryogenic inverter could potentially halve that of an equivalent Si based inverter.


Introduction
The widespread adoption of electric vehicles is steadily progressing, but ambiguity still surrounds the technology needed for large electric transportation, such as aircraft.This presents Original Content from this work may be used under the terms of the Creative Commons Attribution 4.0 licence.Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.
an issue for the aviation industry, since the anticipated growth in air traffic between now and 2050 will further increase CO 2 emissions [1].This has been recognised by companies like Airbus, who are studying hydrogen, H 2 , fuel cell powered aircraft alongside Air New Zealand [2].It is possible that superconducting motors will be the enabling technology for commercial electric aircraft due to their excellent power densities [3][4][5][6].However, these motors, which employ high temperature superconductors (HTS), require cryogenic cooling below a critical temperature to achieve these high power densities.
In an HTS motor driven aircraft if H 2 is used with a fuel cell it would be stored as liquid hydrogen, LH 2 , for greater energy density.The LH 2 , which would be stored below −253 • C, can cool a HTS motor below its critical temperature, so it can serve as both a coolant and fuel.Similar architectures have been proposed in [7][8][9][10], where the Airbus 'ASCEND' [7] program is creating a demonstrator for this dual purpose of LH 2 .In these powertrains, LH 2 cools the HTS motor and HTS cables, and H 2 boiled off from losses is used to cool the power electronics.After use as a coolant, the H 2 can be used to generate electricity via a fuel cell.It is beneficial for the power electronics to transfer as much heat to the H 2 as possible, since fuel cells benefit from a high operating temperature [11].
In such a powertrain the temperature of the power electronics would be cryogenic (<−150 • C).At these temperatures silicon-carbide (SiC) FETs [12][13][14] and IGBTs [15,16] tend to have an increase in conduction losses due to a higher R DS(ON) while silicon (Si) FETs [17,18] and gallium nitride (GaN) high electron mobility transistors (HEMTs), [19][20][21][22][23][24] have reduced conduction losses.However, carrier freezeout limits the R DS(ON) reductions of Si devices in comparison to GaN devices.Although unaffected by carrier freezeout, the R DS(ON) reductions of GaN HEMTs at cryogenic temperature are strongly dependent on the technology used to achieve enhancement mode, E-HEMT, behaviour [22][23][24].The reasons for these changes due to gate behaviour have not yet been explained in commercial power devices which is critical to understand in order to design converters to operate at cryogenic temperature.
Another important point in the literature on cryogenic power electronics is the characterisation of inductor cores.In some work it was shown that ferrite [25,26] and nanocrystalline cores [25,27] have higher losses in liquid nitrogen (LN 2 ) (i.e.77 K or −196 • C).In contrast, in other work the core losses of some nanocrystalline materials have been shown to remain unchanged when cooled from RT to −196 • C [28].This suggests that there is variability in the core loss of these materials depending on the manufacturer, or the experimental setup.The method used to characterise these cores to date has also relied on the classical two winding method.However, nanocrystalline and ferrite cores can have a low permeability, especially at cryogenic temperatures, which can increase phase errors between measured currents and voltages.To reduce this error cancellation methods can be used [29][30][31], but these methods have yet to be applied to nanocrystalline cores, or cryogenic core loss characterisations.
In contrast to inductors, the behaviour of capacitors at cryogenic temperatures is generally well understood [32,33].Film and ceramic capacitors are the most stable with temperature, and the change in equivalent series resistance (ESR) is minimal.The capacitor characterisations to date are in agreement between different publications, which confirm that with proper selection changes in capacitor behaviour will be minimal in comparison to other components [32,33].
Several power converters, which are designed to be operated at cryogenic temperatures have already been reported in the literature [18,34].In [18] Si switches were used to develop a 40 kW three level ANPC inverter, where the authors demonstrated a 30% reduction in losses at −196 • C in comparison to room temperature.However, the losses that would arise from a filter inductor are not considered, and the driver I.C.s are not in the same enclosure as the power modules.In [34] a 1 kW three level flying capacitor inverter was presented, where a ferrite core is used for its filter inductor.It was shown that although the conduction losses when operated down to −60 • C are reduced with GaN E-HEMTs, the inductor core losses become dominant with decreasing temperature.The temperature range was also limited by the driver I.C. used.A cryogenic GaN based, two level current source inverter operating at 77 K has also been proposed [35].In this design an efficiency improvement of 0.7% was measured between RT and CT, but the reported experimental results are limited to 300 W and the total efficiency of the converter is not given.In addition, a loss distribution is not presented and the impact of using a CT inductor is not explored.Although, recently there has been an increasing number of publications in this field, these designs usually either use RT inductors, or the efficiency is low [36], or the output power is less than 1 kW [37].
A number of system level studies have also been proposed, where the operating conditions of the power electronics in a cryo-electric aircraft have been discussed [38][39][40][41][42].In [38] the architecture of a cryo-electric aircraft is discussed, where the power electronics driving the HTS motor are assumed to be operating between 20 K to 120 K, and IGBTs are suggested for use as switches as they are relatively easy to drive.In [39,40] the DC/AC inverter is assumed to operate between 40 K and 120 K over the course of a flight, and based on the Airbus ASCEND architecture [42] the power electronics efficiency, including filtering, is expected to be ⩾99.41%before 2030 with a power density ⩾31.35 kW kg −1 .In the NASA backed CHEETA programme [41] similar operating temperatures are expected for the power electronics, being cooled at 30 K to 50 K using LH 2 .
Although there are many existing publications on the selection of power electronics components for cryogenic temperatures, the findings have not been translated into the efficiency benefits which are expected in a cryogenic power converter.The goal of this paper is to verify existing experimental results reported in the literature, as well as to identify and develop new methods of characterising devices at cryogenic temperatures to allow for better cryogenic power converter designs.This paper focuses on experimentally characterising the conduction loss of GaN and Si switches at cryogenic temperatures, and the core losses of nanocrystalline and ferrite cores at cryogenic temperatures.In section 2 the conduction losses are characterised using a standard circuit for static measurements of GaN and Si devices.In section 3 new characterisation methods are introduced to help explain and model the R DS(ON) reductions observed in the GaN E-HEMTs under test.In section 4 a core loss characterisation method called partial cancellation is modified to characterise the core losses of two different nanocrystalline cores and one ferrite core at cryogenic temperatures.In section 5 there is a brief discussion of the results in the context of a three phase motor drive, which is followed by a conclusion in section 6.

Conduction loss of switches
The equivalent on resistance, R DS(ON) , is used as a measure of conduction loss in a switch.To measure R DS(ON) at cryogenic temperatures LN 2 was used to cool each component down to −196 • C. A printed circuit board (PCB) was developed for each type of component tested and both the current through and voltage across each device was measured using Kelvin connections to evaluate R DS(ON) .The test circuit and experimental setup are shown in figure 1.A drain current, I D , of 1A DC was used in each experiment, where the voltage across the device and its temperature were measured using a PT-104 data logger, which has a measurement accuracy of 15 µV and 0.015 • C respectively.I D was selected as 1 A to ensure minimal self heating of the device under test, while simultaneously establishing a measurably large voltage drop across the device channel.Since the self heating of the devices were low during testing it meant that pulsed measurements were not necessary.VI curves of each device were also taken up to 20 A to ensure the R DS(ON) would not vary significantly with current when submerged in LN 2 .Each device was cooled through LN 2 vapour over 15 min to avoid any damage that may occur due to thermal shock, which was achieved by suspending the devices above the LN 2 bath.As the devices were suspended above the LN 2 bath, their temperature as well as drain to source voltage, V DS , were logged using the PT-104 data logger.A P0K1.202.3FW.B.007 temperature sensor was placed on, or as close as possible, to the thermal pad of each device to measure temperature.The data logged for temperature and V DS for Q2 is shown in figures 2(a) and (b) respectively.Since the temperature of the devices decrease very slowly due to the LN 2 vapours, there is little variability in the temperature between measurements.The sampling rate of the PT-104 data logger is 10 samples per second for both temperature and V DS , which allows their changes to be tracked quickly given the slow temperature decrease.There is a sudden decrease in temperature between approximately −150 • C and −196 • C in figure 2(a) when the sample is submerged in LN 2 , but at this point the  2. Each device listed in tables 1 and 2 was thermally cycled approximately three to five times per device and it was found the R DS(ON) reductions remained the same across all tests.

GaN E-HEMTs
GaN HEMTs are normally on devices that conduct through a two dimension electron gas (2-DEG).This 2-DEG is formed by the piezoelectric effect due to strain between the AlGaN/GaN layers.Modifications to the gate are required to ensure the device is normally off (i.e.enhancement mode operation).
The simplified structures of commonly used gate technologies are given in figure 3, where the 2DEG is on the GaN side for all devices tested.The device Q1 uses the recessed gate structure in figure 3(a) to create a normally off behaviour by thinning the AlGaN/GaN layer beneath the gate.This reduces the piezoelectric effect and hence the 2DEG, which creates an open circuit beneath the gate until a sufficient V GS is applied.
The structure of a generic p-doped GaN (p-GaN) gate is shown in figure 3(b).These devices create normally off behaviour by placing a layer of p-GaN at the gate which depletes the 2-DEG beneath the gate.If an ohmic contact is used as in Q3 and Q4, the device is turned on when the gate current (I G ) is high enough to deplete the p-GaN layer.If a Schottky contact is used as in Q2, Q6 and Q7, the turn on process is controlled by voltage rather than current.
Q5 uses cascode configuration, where an Si FET is in series with a normally on GaN HEMT as shown in figure 3(c).This means the threshold voltage is set by the Si FET making the device normally off.
To confirm the gate structure of each device given in table 1, the threshold voltage, V TH , change at cryogenic temperature was measured and compared to those from [22] for devices from the same manufacturer with similar max V DS , I D ratings.A selection of V TH measurements are shown in figure 4, and the change in V TH compared to the results of [22] are shown in table 3. It can be seen that trends in gate behaviour are very similar, with cascode devices, Q5, and ohmic p-GaN devices, Q3, showing an increase in V TH at −196 • C, and the Schottky p-GaN devices, Q6 and Q7, showing a decrease in V TH at −196 • C. The ohmic p-GaN and cascode devices can be differentiated based on the size of V TH , where a cascode device has a large value of V TH due to the series Si MOSFET controlling the device turn on.
For each GaN E-HEMT in table 1 its normalised R DS(ON) change with temperature is shown in figure 5.The impact of gate technology on cryogenic performance is clear.Devices using an ohmic p-GaN gate had a parabolic shaped change in  The normalised R DS(ON) of the Schottky p-GaN device tested in [22] (GS1) is 0.42 at 200 K.In figure 5 at 200 K the normalised R DS(ON) of Q2 reaches 0.35, Q6 reaches 0.27, and Q7 reaches 0.25.Comparing all of these results shows that the R DS(ON) of Schottky p-GaN devices depends greatly upon the specifications of the device under test, as all of these devices are from the same manufacturer and use the same gate type.The current and voltage ratings of these devices have an influence on the rate of R DS(ON) reductions, as they change the area and length of the 2DEG.This will be discussed further in section 3.
Considering the ohmic p-GaN devices in [22], both devices tested have a normalised R DS(ON) of ≈0.5 at 77 K, whereas in this paper the normalised R DS(ON) is ≈1 at 77 K.This difference is attributed to an increase in the internal resistance of the ohmic gate, R P , which causes the sizing of the gate resistor, R G , as shown in figure 1(a), to have a greater influence on the device turn on process.This point is discussed further in section 3, where the ohmic p-GaN devices are tested with varying gate sizes, and it is found that the smallest value of R G achieves the greatest R DS(ON) reduction in LN 2 .
Three samples of devices with the most promising gate technologies, Q1 and Q7, were tested to gauge the variability in R DS(ON) reductions at cryogenic temperatures, as shown in figure 6.For Q1 the spread of R DS(ON) in LN 2 is lower than at RT, while for Q7 the spread of R DS(ON) in LN 2 is slightly larger than at RT.In both cases the variation of R DS(ON) and its reductions with temperature are minimal.This suggests that variations between GaN devices will likely not overshadow  the trends in gate behaviour shown in figure 5, and the maximum possible R DS(ON) reduction with temperature will not significantly vary from device to device.

IGBT, Si, and SiC devices
The normalised R DS(ON) change with temperature for the Si devices listed in table 2 is shown in figure 7. The Si MOSFET, S1, is the best performing device, as its LN 2 R DS(ON) is only approximately 30% of its RT value.The minimum R DS(ON) of S1 is reached at approximately −150 • C, where it is 25% of its RT value after this point it increases, which is possibly due to carrier freezeout.Although the Si-superjunction (SJ) MOSFET, S2, has good performance at higher temperatures, there is a significant increase in R DS(ON) below approximately 150 • C. The SiC device, S3, is clearly not optimal for cryogenic environments either, since it has far higher conduction losses when compared to its RT R DS(ON) .Although the IGBT device, S4, has increased conduction losses, it is not to the same extent shown with S3.
For the Si MOSFET that was tested it was found that its R DS(ON) did not increase appreciably once it reached −196 • C, which is in agreement with the existing literature [17,43].Considering the Si SJ device, S2, its R DS(ON) increases significantly below −150 • C, which has not been observed in existing literature [18].A possibility for this behaviour is that S2 is unable to fully turn on due to an increase in V TH with reducing temperatures, since the R DS(ON) increase observed in this device is well above other Si SJ devices that have been characterised in the literature [18,43].
Since S1 and S2 were the best of the devices in figure 7, their variations in R DS(ON) reductions are shown in figure 8 as was done with the GaN E-HEMTs.In comparison to the GaN devices in figures 6, S1 and S2 have even lower variability.The maximum deviation from the median in either case is only ≈ 1%, where as this was as high as 6% with Q1.All of the devices in both figures 6 and 8 shows that the spread of variability of R DS(ON) between RT and LN 2 remains roughly the same.

GaN E-HEMT gate behaviour
The results in figure 5 show that with certain GaN E-HEMTs significant R DS(ON) reductions are possible in LN 2 , but the reason for why this varies so much between different gates requires further investigation.A breakdown of the measured R DS(ON) for a generic p-GaN E-HEMT is shown in figure 9.The total resistance can be expressed as, where R CT is the total contact resistance, R 2DEG is the combined resistance of the 2-DEG from the gate to the drain and gate to the source, and R CH is the resistance directly beneath the gate.R CT can be expressed as the sum of source contact resistance, R CS and the drain contact resistance, R CD , while R 2DEG can be expressed as the sum of source to gate 2-DEG resistance, R 2DEGS , and the drain to gate 2-DEG resistance, R 2DEGD , As defined in [44], R CH is given by, where L G is the gate length, µ i is the electron mobility, n i is the 2DEG density and W is the width of the channel, while q is the electron charge.The subscript i denotes the temperature at which R CH is evaluated.In this equation µ i n i is also a function of the gate-source voltage, V GS , and therefore, where k i is a fitting parameter, and ∆V = V GS − V GS(th) .This means that if V GS is varied in small increments beyond the gate-source threshold voltage, V GS(th) , then R CH can be found, since it can be assumed that R 2DEG and R CT are mostly unaffected by V GS .Linear regression can be used to find k i by fitting a model to measurements of R DS(ON) against 1/∆V when the device under test is fully turned on.The gradient of the fitted linear regression would be the inverse of k i for the device under test at a specific temperature.The ratio of k i at two different temperatures, will then be, If it is assumed that when fully turned on µ i and n i are uniform between R CH and R 2DEG then, Here L GS and L GD are as shown in figure 9.Under these assumptions κ m should also represent the change in R 2DEG with temperature.The y-axis intercept of a R DS(ON) vs 1/∆V curve, R DS(intercept) i , represents R CT + R 2DEG and therefore, By comparing κ r to κ m it is now possible to further investigate the total R DS(ON) change.If κ r ≈ κ m then it can be inferred that R CT is small.In contrast, if κ r < κ m then it follows that R CT is a noticeable part of the total R DS(ON) .This method cannot predict the exact change in n i and µ i , but it is useful for understanding device trends and behaviour between room and cryogenic temperatures, which will assist in device selection.condition is κ r ≈ κ m , while for Q2 the condition is κ r < κ m .These devices are both from the same manufacturer and use a Schottky p-GaN gate.So this difference is hypothesised to occur due to differences in maximum drain-source blocking voltage, V (BL)DSS , between the two devices.Commercially available GaN E-HEMTs use a lateral structure, where high V (BL)DSS ratings are achieved by lengthening the 2-DEG to separate the drain and source pins.For a device with higher V (BL)DSS , R CH will then be large relative to R CT .This means that a larger R DS(ON) reduction can achieved using a single HV GaN E-HEMT, rather than multiple LV devices connected in series.This matches the trends shown in figure 5.
Applying this method to Q1 also provides insight into the behaviour of the recessed gate device.The linear regression fit to experimental R DS(ON) measurements of Q1 is shown in figure 10(c).In contrast to Q2 and Q7, the condition is κ r > κ m .Since the region of 2-DEG is thinned beneath the gate of Q1 this means the resistance of this region is high relative to the rest of the 2-DEG.This explains why Q1 has a lower R DS(ON) reduction than Q2 even though they have similar V (BL)DSS ratings.
The above method cannot be applied to Q3 and Q4 due to the change in turn on process observed with ohmic p-GaN gates in figure 5.The unique behaviour of Q3 and Q4 can instead be supported by investigating the R DS(ON) breakdown of figure 9 in relation to the total gate resistance (R GT ).R GT can be thought of as a resistance formed by an external gate resistor R G and the resistance presented by the ohmic p-GaN layer, R P , R P is dependent on temperature, and the turn on of the device is dependent on the current through R P .If R P increases then a higher V GS is needed to generate the desired I G .This makes it difficult to reach the threshold current, I G(th) , which in turn prevents the device from turning on and causes R DS(ON) to increase.Although Schottky p-GaN devices would suffer from similar low temperature effects, they are voltage controlled rather than current controlled.This means that the effects of an increased R P manifest in the form of an increased V GS(th) in Schottky p-GaN gates, while the I G requirements are negligible.
Results supporting this theory are shown in figure 11(a).The curves illustrate the change in R DS(ON) with temperature for Q3 at different values of R G .When the device is cooled, if R G is large then I G is not high enough to overcome I G(th) .A net R DS(ON) reduction of ≈ 50% can be achieved at about −160 • C if R G is lowered to 1Ω.Setting R G = 0Ω demonstrates similar reductions, although the relationship with temperature is difficult to measure due to self heating from the high gate current.Importantly these effects are not observed in the Schottky p-GaN devices of figure 5, where since the value of V GS is much higher than V GS(th) in the first place it means the increase in V GS(th) cannot be observed in the change in R DS(ON) .In figure 11(b) the increase in I G for Q3 at −196 • C and its relationship to V DS(ON) is shown.The increase of R P against temperature is measured directly in figure 11(c) when V GS = 6V and R G = 50Ω.This shows that R P is effectively doubled at −196 • C, and a sharp increase in R P occurs at ≈ −125 • C.These increases in R P and the increased I G(th) shown in figure 11(b) are hypothesised to occur due to carrier freezeout in the p-GaN layer, however further investigation is required to pinpoint the root cause of failure.
These results make it clear that ohmic p-GaN gates are not viable for use at cryogenic temperatures.Currently only minimal reductions in R DS(ON) are possible, and to do this a high I G is required, which will cause significant losses at the gate.
Comparing all of the devices shows the optimal GaN E-HEMT technology to use at cryogenic temperatures are Schottky p-GaNs.This is because they are available in with higher V (BL)DSS ratings and not limited by R CH , which is why they had the most significant R DS(ON) reduction of all GaN E-HEMTs tested.

Inductors
The conventional two winding method is typically used to characterise core loss in magnetic cores [27].In this method, the magnetic field strength (H) in a core under is calculated by exciting a winding that has N 1 number of turns with a current i 1 (t) since, Here l m is the magnetic path length of the core under investigation.flux density (B) in this core is found by measuring the voltage v 2 (t) induced across a second winding that has N 2 number of turns over a single time period T p since, Here A e is the effective cross-sectional area of the core.The energy lost in the core can then be found by integrating the area within the BH curve, This assumes the current and voltage measurements will have no phase error in them.In a practical setup this is impossible to avoid, since component interconnections, probes, and the shunt resistor used to measure i 1 (t) will all have parasitic inductances.The error in power measurement that results from this phase error is given as [30], where ∆φ p is the phase discrepancy caused by the parasitic inductance of the measurement setup, and φ i is the phase difference between v 2 (t) and i 1 (t).Inspection of (13) shows that when the quality factor of the core under test is high, then ∆φ p will be amplified.
To account for this error, the partial cancellation method proposed in [30] can be used.However, this method was developed for ferrite cores and is difficult to apply to nanocrystalline cores due to their significantly high relative permeabilities, µ r .The µ r values of nanocrystalline are in the range of 10 000-100 000, leading to a very high inductance, L m , which needs to be partially cancelled using C s .The resulting reactance of the partially cancelled winding is very high, and cannot be easily driven through a power amplifier to generate the required i 1 (t).Therefore, this paper proposes a modification, where by the partially cancelled winding is parallel compensated using the capacitor C p as shown in figure 12. C p is chosen such that, As shown by v in (t) in figure 12, a power amplifier is used to excite a transformer which then steps up the voltage to generate the required excitation current i 1 (t) through L m .The purpose of the shunt resistor, R s , is to increase the power factor seen by v in (t) The core under test was placed inside an LN 2 container as shown by figure 13 to evaluate core losses at −196 • C. The cores under test are listed in table 4. The voltage across the sense winding, v 2 (t), and the cancellation capacitor, v c (t), is measured using Keysight N2790A differential probes.The current through the core, i 1 (t), is measured using a Keysight N2780A current probe.The core loss calculation still follows the partial cancellation method [30], where the total core loss measured is given by, P core + ∆P core = P core + V 2 sin(φ i )I 1 ∆φ p (15) where P core is the actual core loss, and ∆P core is the error in core loss measurement.The power dissipated in C s is given by, where the measured P Cs represents the error in power measurement across C s .By comparing ( 15) to ( 16), it can be seen that ∆P core is proportional to P Cs .The constant of proportionality between the two terms, k, is given as Since φ i cannot be measured, a small phase shift, φ ′ p , is introduced to the measurements of current i 1 (t), which results in i 1 (t) ′ , to calculate k using, The phase shift of φ ′ p is introduced to the current waveform using a MATLAB program, which is also used to compute the core losses measured using partial cancellation.For further information a detailed derivation of k can be found in a prior paper which covers the partial cancellation method [30].
The permeability changes measured for three cores, referred to as L1, L2 and L3, are shown in figure 14 over a range of frequencies.At lower frequencies the nanocrystalline cores, L1 and L2, have a similar change µ r , however at high frequencies the difference in µ r is much lower for L2.Both of the nanocrystalline cores maintain their µ r better than the ferrite core, L3, when submerged in LN 2 .BH curves at 25 • C and • C are shown in figure 15.For all of the cores the saturation flux density (B sat ) is increased which means they can operate at higher currents.It can also be observed that the area of the BH curve for L2 and L3 is noticeably larger at −196 • C compared to 25 • C, which suggests that these cores will have higher losses at cryogenic temperatures.The difference in core loss power density (P v ) is shown in figure 16      which means operating inductors under cryogenic conditions is possible at higher flux densities compared to at 25 • C. Since L1 was the best performing core, measurements of its core losses up to 50 kHz were fit to the Steinmetz equation, which is of the form, The plot shown in figure 17 summarises how P v of L1 changes with B and f.This shows that as frequency increases the core losses will begin to increase significantly.The 25

Theoretical motor drive case study
Using the experimental component characterisations presented in the preceding sections, the switch losses of a power converter at cryogenic temperatures can be theoretically assessed.For this purpose, a 500 kW three-phase inverter in an HTS motor powertrain is used as case study, which is illustrated in figure 18.The goal of this analysis is to compare the benefit of using GaN switches in a cryogenically cooled inverter, to a Si based room temperature inverter.As given in table 6, a  GaN and an Si inverter converter are compared as 'Case 1' and 'Case 2', respectively, since IGBTs and SiC devices do not work well under cryogenic conditions.The components selected for the case study are listed in table 5.The switching losses are estimated using datasheet values and changes in V TH measured in section 3. The inverter is assumed to be operating with a DC bus voltage, V DC , of 1 kV, at a switching frequency, f s , of 50 kHz to generate a 1 kHz fundamental frequency, f o .To reach the desired blocking voltage, V DC , the R DS(ON) of the switches are scaled based on their maximum V DS as per, N series > V DC V DS(MAX) (20) where N series is the number of switches needed in series to reach the desired V DC .Similarly, to meet the output current requirement, I o , of the inverter, R DS(ON) is scaled based on each switches maximum I DS as per, N parallel > I DS I DS(MAX) (21) where N parallel is the number of parallel switches needed.The scaled resistance for an effective switch is calculated using, The conduction losses are then given by, Using the approach taken in [34], the switching losses are also estimated.Based on ( 20)-( 23), estimates of the total switch loss, P sw , are shown in figure 19 for Cases 1 and 2 respectively, considering the inverter shown in figure 18. Clearly the GaN based inverter has far less losses compared to the Silicon MOSFET inverter, which is due to lower switching and conduction losses in the GaN inverter at both RT and LN 2 .However, in practice connecting the GaN devices in series and parallel will present significant challenges, which is one of the main factors complicating their immediate use within an HTS motor drive.In addition to reduced switch losses, the reduced losses from a nanocrystalline core would also be a significant improvement upon existing attempts at cryogenic filter inductors [28].However, further work needs to be done to identify the filtering requirements for an HTS motor, as well as requirements for scaling the filter inductors to a high power level.

Conclusion
In this article, a selection of switches, and magnetic cores were evaluated in a cryogenic environment.It was shown that GaN E-HEMTs using Schottky p-GaN gates, and Si FETs have the lowest conduction losses in LN 2 .Furthermore, new experimental techniques were introduced which allowed for a more in depth understanding of the gate behaviour of GaN E-HEMTs in LN 2 , showing that R DS(ON) reductions with temperature depend on the V (BL)DSS of the switch.The behaviour of ohmic p-GaN devices were also studied further than done before in previous work, where it was shown the R DS(ON) in LN 2 can be reduced by using a smaller value of R G , although this leads to too large of an I G to be feasible in practice.An improved measurement circuit was also introduced for core loss characterisation, which allowed for magnetic materials to be characterised in LN 2 without phase errors that would have impacted the accuracy of previous cryogenic core loss measurements.The methods presented in this paper provide new and useful insights into the selection of components for cryogenic power electronics.This was illustrated through a theoretical case study of switch losses in a three phase inverter, where the losses of GaN based cryogenic inverter were half that of an equivalent cryogenic Si MOSFET based inverter.

Figure 1 .
Figure 1.(a) Test circuit for measuring R DS(ON) .(b) Example characterisation PCB showing a selection of GaN E-HEMTs.(c) Experimental setup.

Figure 2 .
Figure 2. Example of data logging for Q2 (a) temperature and (b) drain to source voltage.

Figure 7 .
Figure 7. Normalised R DS(ON) change with temperature for Si based switches.

Figure 9 .
Figure 9. Equivalent circuit for total on resistance measurements.
The experimentally measured R DS(ON) of Q7 and Q2 at both RT and −196 • C are shown in figures 10(a) and (b), respectively.Based on the linear regression fits shown, for Q7 the

Figure 11 .
Figure 11.(a) Change in R DS(ON) with Tc & R G .(b) Change in V DS with I G at R G = 0Ω, Tc = −196 • C. (c) Increase of R T with Tc at R G = 50Ω.

Figure 12 .
Figure 12.Equivalent circuit of partial capacitive cancellation method.

Figure 18 .
Figure 18.Three phase inverter considered in loss analysis.

Figure 19 .
Figure 19.Switch losses in GaN and Si based converter at different temperatures.

Table 2 .
Si based devices tested in LN 2 .
R DS(ON) has already flattened out, so there is minimal change in the measurements of V DS as shown in figure2(b).A summary of each GaN E-HEMT tested is given in table 1, and Si based switches are given in table

Table 3 .
GaN threshold voltage change in LN 2 .
begins to negate these reductions as temperature decreases further.It is clear the most promising devices for applications in cryogenic environments use recessed gate and Schottky p-GaN gates.
Figure 13.Experimental setup for core loss characterisation.
• C and −196 • C Steinmetz parameters for both L1 and L2 are shown in table 5.At −196 • C the α for L1 remains the same while for L2 it increases, from which it can be inferred that L2 will have more severe core losses at high frequencies at −196 • C.

Table 6 .
Cryogenic three phase inverter specifications.