Understanding of multiway heat extraction using peripheral diamond in an AlGaN/GaN high electron mobility transistor by electrothermal simulations

High-power operation of high electron mobility transistors (HEMTs) is limited due to a variety of thermal resistances in HEMT devices that cause self-heating effects (SHEs). To reduce SHEs, diamond heat spreaders integrated in the device have proven efficient in extracting heat from the device. In this report, we use electrothermal technology computer-aided design simulations to demonstrate a qualitative understanding of multiway heat extraction utilizing diamond heat spreaders to improve HEMT thermal performance at high DC output power densities (∼40 W mm−1). The impact of each heat extraction pathway is understood while considering the thermal boundary resistance between the diamond/GaN heterointerface and optimization of the GaN buffer layer thickness. Using these findings, we simulate an AlGaN/GaN HEMT device operating at 40 W mm−1 DC output power and demonstrate significant reduction in the temperature.


Introduction
Gallium nitride (GaN), with its exceptional material characteristics of high electron mobility, wide electronic band gap and high electron saturation velocity, is an ideal candidate for high electron mobility transistors (HEMTs).GaNbased HEMTs have numerous uses in radiofrequency (RF) and power applications [1,2].High-output-power operation of a HEMT is constrained by the elevated device temperature that * Author to whom any correspondence should be addressed.
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arises due to the self-heating effect [3].A device operating at a high power density experiences a large flow of electrons in the two-dimensional electron gas (2DEG), which causes a variety of electron scattering effects that lead to the generation of excess heat [4].Due to the moderate thermal conductivity of GaN, inefficient heat extraction leads to the creation of localized hotspots near the 2DEG at the drain side edge of the gate.Elevated temperature due to localized hotspots degrades the mobility of the electrons in the 2DEG region, thereby limiting the device's current density and output power.Additionally, an elevated device temperature also affects the device's reliability and lifetime [5].Therefore, it is crucial to have an efficient heat spreading mechanism on the device that facilitates a low device temperature.A variety of novel thermal management solutions, such as copper micro-trench dissipators [6], microfluidic micro-channel coolers [7,8] and on-chip diamond heat dissipators [9][10][11][12], have been reported.Among these, on-chip diamond heat spreaders are being actively studied due to the excellent bulk thermal conductivity (TC) (>2000 W mK −1 ) of diamond that provides enhanced thermal performance as an on-chip solution [13].Tadjer et al have demonstrated an N-polar AlGaN/GaN HEMT on a thick polycrystalline diamond (PCD) substrate operating at 56 W mm −1 DC output power density with an average gate-drain access temperature of ∼180 • C [14].Similarly, using all-around PCD, Soman et al have demonstrated 30 W mm −1 DC operation of an N-polar AlGaN/GaN HEMT with a SiC substrate at an average channel temperature of 175 • C [15].While diamond is an excellent heat dissipator, numerous factors can influence the flow of heat within a device, including the distance between the hotspot and the heat dissipator, the configuration of the diamond dissipators and the GaN/diamond thermal boundary resistance (TBR) [16][17][18].Well-conducted experimental and simulation studies have examined the influence of TBR, substrate TC and substrate thickness on the thermal performance of GaN HEMTs [19][20][21][22].However, reports on trend analysis of multiway heat extraction using multiple diamond heat dissipators along with design optimization for high-DC output power density (40 W mm −1 ) HEMT operation are limited.
In this article we report a qualitative understanding of a multiway heat extraction strategy using single crystalline and PCD integration in an AlGaN/GaN HEMT operating at 40 W mm −1 power dissipation.Peak device temperature trends are analyzed while varying TBR, the optimum distance between the hotspot and heat dissipators, heat spreader position and heat sink configurations.

Simulation details
A conventional AlGaN/GaN device structure, as shown in the inset to figure 1, is utilized for the simulation.Detailed geometrical parameters of the device structure are listed in table 1. Substrate, sidewall and top diamond layer modifications are made to this conventional device structure, as shown in figures 2(a), 4(a) and 6(a)-9(a).In these figures, PCD is used for the sidewall and top heat spreaders whereas singlecrystalline diamond (SCD) is used as a substrate heat spreader.A range of TBRs at the GaN/diamond interface are simulated to understand the heat flow inside the device.
To account for the TBR at all the GaN/diamond interfaces, a 5 nm thick TBR layer is added to the structure.To simulate different TBRs at the GaN/diamond interface, the thermal conductivity of the TBR layer is calculated for each TBR value using the formula TC = thickness/TBR value [23].The source (S) and drain (D) regions are heavily doped n-type GaN with a donor concentration of 10 20 cm −3 .A gate metal of length L g with a work function (ϕ m ) of 3.5 eV forms a Schottky contact with the AlGaN layer.The DC characteristics of the illustrated AlGaN/GaN HEMTs are obtained via twodimensional (2D) electrothermal simulations performed using the BLAZE model in Atlas Silvaco technology computeraided design (TCAD) software.We utilize material parameters as reported in various experiments and simulations in

Material
Thermal conductivity AlGaN/GaN 130 × (300/T) 1.43 [28] Thermal boundary layer Calculated using the formula X (300/T) 1.43 where X = 1.61-0.25 PCD (cross-plane) 600 × (300/T) 1 [29] PCD (in-plane) 400 × (300/T) 1 [29] SCD 1800 × (300/T) 1 [29] SiC 420 × (300/T) 1.5 [30] SiN 2 [31] the literature.FERMI, DRIFF.DIFF, CONSRH and AUGER models are utilized to account for carrier transport, carrier statistics and carrier generation and recombination.Furthermore, JOULE.HEAT and LAT.TEMP models are adopted to simulate the generation of a localized hotspot in the 2DEG and heat transfer from the hotspot to other parts of the device.The Dirichlet boundary condition at 300 K necessary to solve heat flow equations is applied wherever the sink is shown in the device structures.Additionally, for simplicity of analysis, heat is only extracted from the boundaries where the Dirichlet boundary condition is declared, i.e. boundaries where a heat sink is attached to the device, and other boundaries are declared as adiabatic in 2D TCAD [24].These models also account for the temperature-dependent thermal conductivity of the layer stack in the AlGaN/GaN HEMT as shown in table 2. Furthermore, the TCs of PCD and SCD considered in the simulation are taken from the experimental literature for that particular thickness [25,26].The GaN TC values used are isotropic since the anisotropic TC of GaN is dominant at temperatures below room temperature [27].The temperature dependence of TBR layer TC is assumed to be like that of GaN.As temperature affects electron mobility, temperature-dependent highfield and low-field mobility models GANSAT and ALBRCT are required.Two-dimensional electrothermal TCAD simulations are less accurate than 3D finite element modeling (FEM), primarily because heat flow equations solved in the 2D domain fail to mimic the 3D process of heat diffusion [32].Additionally, due to limitations of 2D thermal simulations, we have focused more on analyzing the trends in this work.Simulation results in figures 1-5 demonstrate the trends previously reported in experimental and simulation-based works on GaNon-diamond and help to show the correctness of the model for performing a qualitative analysis [19,21,33].Advanced modeling techniques such as 3D FEM can overcome the aforementioned limitations of 2D TCAD.However, 3D FEM simulations are resource intensive and take longer to execute.Furthermore, bias-dependent variation in the Joule heating region cannot be replicated by 3D FEM thermal simulations alone [5].This problem can be tackled by a hybrid simulation strategy using 2D TCAD and 3D FEM modeling [34][35][36].However, the primary motivation of this report is to analyze the trends for multiway heat extraction, therefore focusing more on the qualitative aspects of electrothermal analysis and leveraging the benefits of a 2D TCAD simulator.A detailed quantitative analysis of the present work will be covered in a future report.

Results and discussion
To understand the impact of substrate TC on the thermal performance of the device no TBR layer is added between the GaN buffer layer and substrate as shown in figure 1. Figure 1 illustrates the AlGaN/GaN HEMT simulation results with 1 µm thick GaN buffer layer on 100 µm thick GaN, SiC and SCD substrates.As depicted, the thermal resistance of the SCD substrate device is ∼13.5 and ∼5.5 times lower than the thermal resistance of GaN and SiC substrate devices, respectively.These results unequivocally show a superior heat extraction from the SCD substrate, resulting in an excellent thermal performance.
To understand the impact of TBR on the peak device temperature, the peak device temperature at 40 W mm -1 DC power density for each TBR value (3.1, 6, 10 and 20 m 2 K GW −1 ) is recorded while varying the distance from the hotspot to the GaN/SCD interface.Bringing the GaN/SCD interface closer to the hotspot by reducing the GaN buffer layer thickness can effectively lower the thermal resistance of the GaN buffer layer.However, as reported in other works [37], it has been noted that as the TBR increases the optimal distance between the GaN/SCD interface and hotspot also increases.In figure 2(b), at a TBR of 20 m 2 K GW −1 , the optimal thickness is 1000 nm as the peak device temperature for GaN buffer layer thickness of 1000 nm is lowest at 879 K.However, at a TBR of 3.1 m 2 K GW −1 the optimal GaN buffer layer thickness is 250 nm, showing the lowest peak device temperature of 721 K. Hence it is crucial to optimize the GaN buffer layer thickness based on the TBR value at the GaN/SCD interface.
The GaN buffer layer thickness plays an important role because it reduces the heat flux from localized hotspots by spreading heat laterally in the GaN buffer layer before it reaches the GaN/diamond interface.Thermal contours of devices with varying hotspot to interface distances in figure 3 show that if the GaN buffer layer is too thin, inefficient lateral heat spreading before the GaN/SCD interface is encountered, i.e. a higher heat flux near the hotspot leads to an elevated  lattice temperature in the vicinity of the hotspot [21].On the contrary, if the distance between the hotspot and the interface is increased to enhance lateral heat spreading by making the GaN buffer layer thicker, the additional thermal resistance provided by the GaN buffer layer adversely affects the thermal performance of the device.Such trends of decrease and increase in peak device temperature with increase in GaN buffer layer thickness have also been reported in comprehensive works on near junction thermal transport [16,21,37,38].Therefore, optimization of the distance between the hotspot and interface is necessary to achieve the best thermal performance of the device.Going forward, this optimization is performed for a variety of device structures simulated in this work.
The heat flow in the substrate can affect the performance of the device.Each active device generates heat flux under operation.If these devices are closely packed, the heat flux in the substrate layer will be higher, thereby elevating the substrate temperature.Therefore, if the distance between adjacent devices is increased to reduce the heat flux in the substrate layer, the thermal performance of the device can be improved.Of course, the spacing between the devices involves a tradeoff with packing density on the wafer.For the device structure shown in figure 4(a), an additional 25 µm of space is added beside the conventional HEMT structure to reduce the heat flux inside the substrate.Owing to the reduction in heat flux, a >20% decrease in the peak device temperature is observed for all GaN/SCD interface TBR values.The hotspot to GaN/SCD interface distance and TBR values in figure 4(b) follow a similar trend as in figure 2(b).The thermal contours for the structure in figure 4(a) with different hotspot to interface distances are illustrated in figure 5 and the lateral heat spreading explanation mentioned previously aligns with the results shown.
For further analysis of devices with different heat spreader configurations, the GaN/SCD TBR will be 10 m 2 K GW −1 unless specified otherwise.The TBR value at the interface depends on the integration technique used.The SCD is generally integrated with the AlGaN/GaN HEMT structure by wafer bonding or by direct growth of GaN on top of the SCD [17,39,40].Both techniques lead to a higher TBR value than the record low TBR value reported by Mohamadali et al for a GaN/PCD interface.They reported a TBR of 3.1 m 2 K GW −1 for PCD grown on GaN using a SiN interlayer by microwave plasma chemical vapor deposition (MWCVD) [41].This is the lowest reported experimental TBR value, and is close to the theoretical minimum value of 3.0 m 2 K GW −1 predicted by the diffuse mismatch model [16].Considering a TBR of 10 m 2 K GW −1 for GaN/SCD the lowest peak device temperature of ∼650 K is obtained at a hotspot to interface distance of 750 nm.
To further reduce the temperature, a 25 µm long, 2-3 µm thick PCD is added to the sidewall of the AlGaN/GaN HEMT, as shown in Figure 6(a).Due to the limited thermal conductivity of the GaN buffer layer and GaN/PCD interface being farther than the GaN/SCD interface, 'path 2' shown is figure 6(a) is more thermally resistive than 'path 1'.Therefore, the majority of heat extraction takes place from 'path 1' or the 'bottom of the device' which is a similar heat extraction pathway to that utilized in previous device structures.Figure 6(b) shows a ∼1% reduction in peak device temperature compared with figure 4(b) for a GaN/SCD TBR of 10 m 2 K GW −1 , demonstrating negligible lateral heat extraction.Therefore, to further extract heat from the hotspot an additional heat extraction pathway can be added by adding a heat dissipator on top of the device.
Figure 7(a) shows an AlGaN/GaN HEMT structure with substrate, sidewall and top diamond heat dissipator where the sidewall PCD/GaN TBR is fixed to 10 m 2 K GW −1 , the GaN/SCD TBR is set to 10 m 2 K GW −1 and the top PCD TBR is varied from 0 to 20 m 2 K GW -1 .Having an additional heat extraction pathway reduced the peak device temperature from 640 K to 498 K for a top PCD TBR of 3.1 m 2 K GW −1 .We can see that the optimal distance of the hotspot from the GaN/SCD interface is reduced and moves closer to 500 nm compared with 750 nm for the device structure with only a substrate and sidewall (figure 6(b)).This reduction in the optimal distance can be attributed to the reduced heat flux inside the GaN buffer layer attributed to the presence of an additional heat extraction pathway ('path 2').Similarly, Soman et al have demonstrated heat conduction from the shunt pathway to improve heat extraction from the device [15].Therefore, by using top and substrate diamond heat spreaders the AlGaN/GaN HEMT can operate at significantly lower temperatures with an output power density of 40 W mm −1 .
The presence of sidewall heat dissipators results in minimal advantage unless a heat spreader and/or a heat sink is added on top of the device.When a second heat sink is added to the top of the device, as shown in figures 8(a), and 9(a), the device temperature can be further reduced compared with heat extraction from 'path 1' alone.This reduction can be attributed to the shunt path provided by the sidewall between the top and bottom heat sinks.This shunt path can be used to reduce the sidewall length of 25 µm (figure 7  length can help us to reduce the distance between two adjacent devices on the wafer.This length reduction translates to an opportunity to increase the areal density of devices for a given wafer area. Figure 8(a) demonstrates an AlGaN/GaN HEMT with a PCD heat dissipator of length 6 µm and sidewall thickness of 3 µm.The top sink is attached to the top of the PCD sidewalls.Figure 8(b) illustrates the data when the TBR of the GaN/SCD substrate is varied from 0 to 20 m 2 K GW −1 .The heat coming out from the bottom of the GaN/SCD interface can now be extracted via a shunt path ('path 2') provided by the sidewall PCD, as shown in figure 8(a).For a GaN/SCD TBR of 10 m 2 K GW −1 , there is a ∼180 K reduction in the peak temperature of the device with top and bottom heat sinks with PCD sidewalls compared with a conventional device with only a SCD substrate with a bottom heat sink (figure 2(a)).Optimization of the hotspot to GaN/SCD interface distance is performed for the device in figure 8(a), resulting in a similar outcome to that observed previously, i.e. the optimal distance increases with increase in the TBR.Additionally, there is a reduction in the optimal distance for all TBR values compared with the results shown in figure 2(b).To further reduce the peak device temperature in figure 8(a), an additional heat extraction pathway can be added near the hotspot on the top of the device, as in the device shown in figure 7(a).
Figure 9(a) demonstrates a device structure with top, sidewall and substrate diamond heat spreaders with heat sinks at the top and bottom of the device.It should be noted that the top PCD TBR is of greater importance than the sidewall PCD TBR because of the poor lateral heat extraction at the GaN/sidewall PCD interface.For a device with a GaN/SCD TBR of 10 m 2 K GW −1 and top and sidewall PCD TBRs of 3.1 and 10 m 2 K GW −1 , respectively, operating at 40 W mm −1 power dissipation the peak device temperature recorded was ∼470 K.This enhancement in performance due to top, bottom and side-wall diamond is in agreement with the experimental and simulation-based studies already reported [10][11][12].
Although this study has focused exclusively on electrothermal simulations, in the next section we attempt to discuss how the proposed designs can be experimentally realized.Implementation of the proposed structures can be divided into three main parts, i.e. growth/integration of diamond heat spreaders, processing and packaging.Integration of SCD into AlGaN/GaN HEMTs using wafer bonding techniques is well reported [10,17,42].In this technique, a temporary/sacrificial substrate is bonded on top of processed AlGaN/GaN on the silicon/SiC wafer and holds the wafer during processing.The existing substrate is removed by performing back-side mechanical aberration.Upon removal of the desired material layers, SCD is bonded to the AlGaN/GaN and the temporary substrate is removed from the top [9,43].Once the material stack with the SCD substrate is ready, the device sidewall can be exposed by performing slant mesa etching followed by PCD diamond deposition as reported by Soman et al [15].Many articles have reported the topside growth of PCD diamond by utilizing AlN or SiN as an interlayer [44].Diamond is seeded on this interlayer by performing a nano-seeding step followed by deposition of the PCD using MWCVD.Upon diamond deposition, regular processing steps for metal deposition can be executed.Therefore, by using the aforementioned techniques it is possible to achieve the structures shown in figures 6(a)-9(a).For a top and bottom heat sink configuration Li et al demonstrated the implementation of a doublesided cooling solution for GaN HEMTs which can be used to produce the heat sink configurations illustrated in figures 8(a) and 9(a) [45].Even though there are several growth and processing challenges, such as avoiding surface damage on the top of the device, wafer bow and high residual thermal stress [46], ensuring a voidless GaN/diamond interface [47] and interface robustness [48], among other challenges, these problems are not insurmountable and the thermal management of future generations of AlGaN/GaN HEMT devices can be enhanced.

Conclusion
This article showcases the enhanced steady-state thermal performance of AlGaN/GaN HEMTs achieved via a multiway heat extraction strategy in electrothermal simulations.We illustrate that as the TBR of the GaN/SCD interface increases, the optimal GaN buffer layer thickness also increases; this holds for all the device structures.For device structures with a heat sink just at the bottom, heat spreading in the GaN buffer layer and SCD substrate is increased.Furthermore, we demonstrate that the major role of the PCD wall is to act as a shunt path for heat conduction.When the heat sink is only at the bottom the sidewall provides a shunt path from the hotspot to the substrate via the top heat spreader.For devices with top and bottom heat sinks, however, the side wall acts as a shunt path for heat conduction from the GaN/SCD interface to the top PCD heat spreader via substrate and sidewall PCD.In both cases we demonstrated the operation of an AlGaN/GaN HEMT at 40 W mm −1 DC output power by modifying and optimizing the device structure.

Figure 2 .
Figure 2. (a) A conventional AlGaN/GaN HEMT with a 100 µm thick SCD and 13 µm long substrate.(b) Peak device temperature against varying distance from the hotspot for TBRs of 0-20 m 2 K GW −1 .

Figure 3 .
Figure 3. Thermal contours for the device shown in figure 2(a) with varying hotspot to interface distances for a GaN/SCD TBR of 3.1 m 2 K GW −1 .

Figure 4 .
Figure 4. (a) A conventional AlGaN/GaN HEMT with 100 µm thick SCD and a 63 µm long substrate layer.(b) Peak device temperature against varying distance from the hotspot for TBR values of 0-20 m 2 K GW −1 .

Figure 5 .
Figure 5. Thermal contours for the device shown in figure 4(a) with varying hotspot to interface distances for a GaN/SCD TBR of 3.1 m 2 K GW −1 .
(a)) to 6 µm (figure 8(a)) without a top side dissipator while maintaining a similar operating temperature range.The reduction in sidewall

Figure 6 .
Figure 6.(a) A conventional AlGaN/GaN HEMT with 100 µm thick SCD and a 63 µm long substrate with a 25 µm long, 2 µm thick sidewall PCD heat spreader.(b) Peak device temperature against varying distance from the hotspot for TBR values of 0-20 m 2 K GW −1 .

Figure 7 .
Figure 7. (a) A conventional AlGaN/GaN HEMT with 100 µm thick SCD, a 63 µm long substrate and 25 µm long, 2 µm thick PCD sidewall and 2 µm thick top PCD heat spreaders.(b) Peak device temperature against varying distance from the hotspot for TBR values of 0-20 m 2 K GW .

Figure 9 .
Figure 9. (a) An AlGaN/GaN HEMT with substrate, sidewall and top diamond heat spreaders (b) Peak device temperature for GaN/SCD TBRs of 3.1 and 10 m 2 K GW −1 with optimal distances from hotspot of 100 nm and 2000 nm, respectively.

Table 1 .
List of geometrical parameters of the device.

Table 2 .
Thermal conductivity of the HEMT material stack (T is temperature).