The GaN trench MOSFET with adaptive voltage tolerance achieved through a dual-shielding structure

A novel GaN trench gate vertical MOSFET (PSGT-MOSFET) with a double-shield structure composed of a separated gate (SG) and a p-type shielding layer (P_shield) is proposed and investigated. The P_shield is positioned within the drift region, which can suppress the electric field peak at the bottom of the trench during the off state. This helps to prevent premature breakdown of the gate oxide layer. Additionally, the presence of P_shield enables the device to have adaptive voltage withstand characteristics. The SG can convert a portion of gate-to-drain capacitance (C gd) into drain-to-source capacitance (C ds), significantly reducing the gate-to-drain charge of the device. This improvement in charge distribution helps enhance the switching characteristics of the device. Later, the impact of the position and length of the P_shield on the breakdown voltage (BV) and specific on-resistance (R on_sp) was studied. The influence of the position and length of the SG on gate charge (Q gd) and BV was also investigated. Through TCAD simulations, the parameters of P_shield and SG were optimized. Compared to conventional GaN TG-MOSFET with the same structural parameters, the gate charge was reduced by 88%. In addition, this paper also discusses the principle of adaptive voltage withstand in PSGT-MOSFET.


Introduction
Silicon (Si), as a first-generation semiconductor material, possesses excellent physical and chemical characteristics.The research achievements related to Si have greatly contributed to the development of the integrated circuit field.Currently, power electronic devices are primarily made using silicon Original content from this work may be used under the terms of the Creative Commons Attribution 4.0 licence.Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.semiconductor material.However, the inherent material characteristics of Si result in commercially available devices and chips that have larger sizes and heavier weights, which do not align with the future trends of lightweight and simplified applications.GaN, as a representative of third-generation semiconductor materials, offers several advantages such as a wide bandgap, high electron saturation velocity, high breakdown field, corrosion resistance, and radiation hardness.These properties make GaN more suitable for extreme environments like high temperature and high-frequency applications.GaN has found extensive applications in high-voltage and highpower fields due to its superior characteristics.In terms of bandgap width and breakdown field strength, GaN is approximately three times wider and has a breakdown field strength around 10 times higher than Si.Additionally, in terms of electron drift saturation velocity, GaN is approximately 2.5 times higher than Si [1,2].Therefore, GaN is suitable for devices used in high-frequency, high-voltage, and high-power applications, which can help reduce power consumption in power electronic devices [3,4].Today, GaN is poised to gain a larger market share, particularly in high breakdown voltage (BV) and high-power applications in power systems.In recent years, there has been a surge of research and development in vertical GaN devices, as they hold great potential for future power systems with their high BV and high power capabilities.The vertical MOSFET structure has been widely applied in siliconbased power devices, enabling higher current densities and reduced parasitic effects within a smaller chip area [5,6].Despite the relatively complex manufacturing process, vertical GaN power devices are easier to achieve enhancement mode operation and avalanche breakdown, thus attaining optimal figures of merit (BFOM) [7,8].However, in the off-state, trench gate MOSFET (TG-MOSFET) exhibit extremely high electric fields (E) at the bottom of the trench, which can lead to reliability issues [9].Another drawback is that TG-MOSFET have a thinner gate oxide, which isolates the gate and drain regions.This results in larger gate-to-drain capacitance (C gd ) and charge (Q gd ), leading to increased switching losses in the circuit [10,11].To address the aforementioned issues, a solution has been proposed, which involves introducing a p-type shielding layer (P_shield) in the drift region and incorporating a shielding gate beneath the trench in the gate region [12,13].The P_shield can reduce the peak electric field beneath the trench gate, preventing premature breakdown of the gate oxide layer and thus improving the BV.The Separated Gate Trench MOSFET (PSGT-MOSFET) is a novel device structure that has been applied in SiC TG-MOSFET.It incorporates two electrodes within a single trench gate structure [14][15][16].The upper electrode serves as the gate electrode to control the formation of the conductive channel in the MOSFET, while the bottom electrode separated gate (SG) is connected to the source and grounded.As a result, PSGT-MOSFET reduces C gd and Q gd , enhancing the switching characteristics of the device.
In this paper, we propose a novel GaN-based vertical TG-MOSFET with a SG and P_shield, called the 'P_shield SG Trench MOSFET' (PSGT-MOSFET).The novelty of this work lies in the incorporation of a P_shield in the drift region and the utilization of an additional charge control electrode (SG electrode) in the trench gate.Compared to previous approaches that design the voltage withstand range of the device based on specific operating requirements, the proposed device in this paper features adaptive voltage withstand capability.It can automatically adapt the voltage withstand capacity according to the changes in the operating conditions.The simulations in this work utilized the electron/hole continuity equations, Poisson equation, and appropriate physical models.For a fixed minority carrier lifetime, the Shockley-Read-Hall recombination model was employed along with Auger recombination and avalanche models.Due to the high activation energy of the impurities doped in Gan, an incomplete ionization model is employed.

Device structure and principles
Figure 1(a) depicts the structural schematic of the proposed PSGT-MOSFET.It features a grounded SG (shielding gate) and a P_shield.The P_shield is situated in the drift region, while the SG is located beneath the trench control gate.In the structure, D ps represents the distance from P_shield to P_base, L ps denotes the length of the P_shield region, D ox signifies the distance from SG to the bottom of the gate oxide, and L ox represents the lateral distance from the SG to the trench gate oxide.Figure 1(b) illustrates the structural schematic of a conventional TG-MOSFET.The drift region has a doping concentration and thickness of 5 × 10 15 cm −3 and 8.5 µm, respectively.The substrate has a doping concentration and thickness of 1 × 10 20 cm −3 and 2 µm, respectively.See table 1 for additional detailed parameters.
In the PSGT-MOSFET (figure 1(a)), a P_shield is inserted into the drift region, resulting in the drift region being composed of two segments.Under reverse bias, the insertion of P_shield leads to another electric field peak as the spike point (E P_shield ) in figure 2(c).Therefore, theoretically speaking, with the same N-drift doping concentration, GaN PSGT-MOSFET is expected to achieve higher BV compared to conventional GaN TG-MOSFET.For comparison, the electric field distributions of GaN PSGT-MOSFETs and TG-MOSFETs with the same structural parameters at 1100 V drain voltage are simulated, as shown in figures 2(a) and (b).In addition to the E-field peak at the channel corner, the presence of the P_shield generates another E-field peak at the interface between the P_shield and the drift region.By analysing the Efield distribution at X = 4.0 µm (shown in figure 2(c)) and the E-field peaks at the channel corners (shown in the insets in the middle of figures 2(a) and (b)), it can be found that compared with the conventional TG-MOSFET, the PSGT-MOSFET are effective in suppressing the E-field peaks in the GaN gate oxides at the same drain bias.As a result, the P_ shielding suppresses the premature breakdown of the gate oxide, thereby increasing the BV of the device.
Figure 3 illustrates the capacitance components of the two structures.The PSGT-MOSFET features an SG that serves as a shielding area between the gate and drain, converting a portion of C gd into series-connected C ds1 and C gs1 , as shown in figure 3(a).Therefore, the C gd of the PSGT-MOSFET can be expressed as: 3(c) compares the simulated C gd of the two structures in figures 3(a) and (b).By sweeping V ds from 0 V to 500 V while keeping V gs constant at 0 V, it demonstrates the C-V characteristics [17].The results verified that the presence of SG significantly reduced C gd .Clearly, the MOSFET with the SG structure (figure 3(a)) has a smaller C gd compared to the conventional trench MOSFET without the SG structure (figure 3(b)).The presence of the SG leads to an 82% reduction in C gd .

Results and discussions
In order to understand the influence of the geometric parameters of P_shield and SG on device performance and determine the optimal device structure parameters.We conducted simulations to study the impact of various geometric parameters of P_shield and SG on device performance.For P_shield, we considered parameters such as the distance to P_base (D ps ), length (L ps ), and the principle of achieving adaptive voltage capability.For SG, we considered parameters such as the distance to the bottom of the gate oxide layer (D ox ) and the distance to the sidewall of the gate oxide layer (L ox ).In this study, BV is defined as the drain voltage at which the impulse ionization integral equals 1 or the critical electric field (10 MV cm −1 ) for the ALD-deposited SiO 2 [18].As D ps increases, the peak electric field in the gate oxide layer decreases, which indicates that the further P_shield is from P_base the more effective it is in suppressing the peak electric field (E oxide ) in the gate oxide layer and improving the reliability of the gate oxide layer.However, the larger the D ps value, the smaller the peak electric field at the interface between the shield and the drift region will be.As shown in figure 5(a), this leads to a more heterogeneous electric field distribution in the drift region, which in turn reduces the BV.In addition, by comparing the peak electric field (E oxide ) in the gate oxide layer and the electric field distribution along the Y-axis at X = 4.0 µm for different L ps values, it can be observed that longer P_shield lengths effectively suppress E oxide .On the other hand, the peak electric field at the shielding layer in the drift region may slightly increase.However, this does not affect the increasing trend of BV with the increase of L ps .Indeed, this indicates that longer P_shield lengths can significantly reduce the electric field in the gate oxide, thereby improving the device's voltage withstand characteristics.Figure 4(b) illustrates the variation of specific on-resistance for PSGT-MOSFET.R on_sp increases with the increase of L ps and decreases with the increase of D ps .Therefore, in order to achieve a high Baliga Figure of Merit (BFOM), a trade-off between BV and R on_sp needs to be made.Taking into consideration the goal of achieving high BV, low R on_sp , and good reliability, the parameters D ps = 2.5 µm and L ps = 3.0 µm are selected.

The impact of P_shield position and length on device performance
Figure 4(d) shows the BV and specific on-resistance of the PSGT-MOSFET versus the P_shield thickness (T ps ).As T ps increases, R on_sp gradually increases and BV first increases and then decreases to reach the maximum at 0.5 µm.Considering the optimal BFOM, the T ps is chosen to be 0.5 µm.

The principle of adaptive voltage withstand in devices
After fixing D ps = 2.5 µm, L ps = 3.0 µm and T ps = 0.5 µm for P_shield, the gate and source were grounded, and simulations were conducted at different drain voltages.As shown in figure 6(a), the current curve at different drain voltages is displayed.Analyzing the curve, it is observed that the leakage current is zero at drain voltages of 300 V and 900 V.Only when the drain voltage reaches 1600 V does a leakage current exceeding 1 µA appear.This indicates that the device experiences breakdown at this point.Therefore, the maximum value of the device's adaptive voltage withstand is chosen at the voltage peak of 1500 V, where no leakage current is observed.Analysis of the hole concentration in P_shield under three different leakage currents, as shown in figure 6(b), reveals a significant increase in hole concentration with increasing drain voltage.This is because as the external electric field increases,  Figure 9 describes the effect of D ox and L ox on electron density.In the forward conduction state, the SG, gate oxide layer, and N-drift form an MIS structure.The MIS structure forms a depletion region in the drift region (marked with a white line  at the boundaries of the depletion region), which then creates the JFET resistance.By increasing D ox and L ox , the lateral depletion effect of the MIS structure is weakened, and a wider electron current path is maintained.This helps reduce R on_sp .However, the BV of the device decreases with the increase of D ox and L ox .
Figure 10 demonstrates the relationship between C gd (gateto-drain capacitance) and D ox (gate oxide thickness) and L ox (gate length) in PSGT-MOSFET.With increasing D ox , C gd slowly increases.This is because if the distance between the SG and the control gate electrode is reduced, the shielding effect weakens.Clearly, under the same D ox , C gd significantly increases with increasing L ox .This indicates that C gd is more sensitive to L ox compared to D ox .It means that the positioning of the gate-source overlap is more important when aiming to achieve a smaller C gd .Therefore, the optimized values for D ox and L ox are determined to be 0.3 µm and 0.6 µm, respectively.In the switching losses of power MOSFET, Q gd is crucial [19].In the test circuit with I g = 0.1 mA, I 1 = 5 A, and V ds = 30 V [20], the PSGT-MOSFET has a Q gd of 110 nC cm −2 , which is 88% lower compared to the TG-MOSFET's Q gd of 910 nC cm −2 .This reduction in Q gd indicates that the presence of gate shielding in the SG region significantly reduces parasitic capacitance, allowing for a smaller Q gd to be achieved.Comparing the calculated high-frequency figure of merit (HF-FOM (Q gd × R on ) [21], the PSGT-MOSFET has a value of 6.46 nC•mΩ, which is approximately 3.5 times lower than the TG-MOSFET's value of 22.59 nC•mΩ.This signifies a significant improvement in the PSGT-MOSFET's performance, indicating lower switching losses and better overall efficiency.

Conclusion
The proposed device was analyzed using TCAD and compared with conventional GaN TG-MOSFET.Based on the traditional device structure, a segregated trench gate structure was proposed, and a shield layer (P_shield) was inserted at the bottom corners of the trench gate.The shield layer helps reduce the peak electric field in the gate oxide layer, significantly improving the reliability of the device's gate oxide layer and increasing the BV.The segregated gate structure reduces C gd and Q gd of the device by 82% and 88%, respectively, optimizing the switching characteristics of the device.Through simulation, the effects of SG (segmented gate) and P_shield geometric parameters on the breakdown characteristics and specific on-resistance (R on_sp ) of GaN PSGT-MOSFET were studied.The positions and lengths of SG and P_shield were optimized to maximize the device's BFOM and HF-FOM.Last but not least, simulation results reveal that the presence of P_shield enables the device to exhibit adaptive voltage withstand capability.Under different drain voltages in various operating scenarios, varying external electric fields enter the device.Consequently, different numbers of holes in the P_shield region gain enough energy to break free from the ionic bonds and become free-moving ions that can conduct electricity.This, in turn, affects the ionization concentration of P_shield, effectively modifying its doping concentration and achieving adaptive voltage withstand capability.

Figure 4 (
Figure 4(a) shows the variation of BV of GaN PSGT-MOSFET with different positions (D ps ) and lengths (L ps ).Figure 4(c)

Figure 2 .
Figure 2. (a) and (b) represent the two-dimensional electric field distribution of the conventional GaN TG-MOSFET and GaN PSGT-MOSFET, respectively, at a breakdown voltage of 1000 V.They are magnified to show the electric field distribution near the trench corner.(c) shows the electric field distribution along the Y-axis at X = 4.0 µm for the conventional GaN TG-MOSFET and GaN PSGT-MOSFET at a breakdown voltage of 1000 V.
Figures 8(a)  and (b) demonstrates the impact of D ox and L ox on the BV and specific on-resistance (R on_sp ) of PSGT-MOSFET.Figure9describes the effect of D ox and L ox on electron density.In the forward conduction state, the SG, gate oxide layer, and N-drift form an MIS structure.The MIS structure forms a depletion region in the drift region (marked with a white line

Figure 4 .
Figure 4. (a) The impact of Dps and Lps on breakdown voltage, (b) The impact of Dps and Lps on specific on-resistance, (c) The impact of Dps and Lps on the peak electric field in the gate oxide layer, (d) Effect of P_shield thickness on breakdown voltage and specific on-resistance.

Figure 7 .
Figure 7. (a) When Dps, Lps, and Tps are fixed at 2.5, 3.0, and 0.5 µm, the relationship between the BV of the GaN PSGT-MOSFET and the doping concentration of P-shield was simulated.(b) The relationship between the Ron_sp of the GaN PSGT-MOSFET and the doping concentration of P-shield.

Figure 8 .
Figure 8.(a) Represents the variation of BV and Ron_sp as functions of Dox with Lox set at 0.6 µm, (b) represents the variation of BV and Ron_sp as functions of Lox with Dox set at 0.4 µm.

Figure 10 .
Figure 10.The dependency of C gd (at V ds = 500 V) of PSGT-MOSFET on Dox and Lox.

Figure 11
Figure 11 displays the gate charge simulation waveforms of the designed PSGT-MOSFET and the traditional TG-MOSFET, with the simulation circuit illustrated in illustration.In the switching losses of power MOSFET, Q gd is crucial[19].In the test circuit with I g = 0.1 mA, I 1 = 5 A, and V ds = 30 V[20], the PSGT-MOSFET has a Q gd of 110 nC cm −2 , which is 88% lower compared to the TG-MOSFET's Q gd of 910 nC cm −2 .This reduction in Q gd indicates that the presence

Figure 11 .
Figure 11.The Q gd values of PSGT-MOSFET and TG-MOSFET, where the extracted Q gd values are 110 and 910 nC cm −2 , respectively; the illustration displays a simulated circuit.

Table 1 .
Device parameters during simulation.