Low-resistive gate module for RF GaN-HFETs by electroplating

This paper presents a novel approach for reducing the gate resistance (R g) of K and Ka-band GaN HFETs with 150 nm gate length through a new gate metallization technique. The method involves increasing the gate cross-section via galvanic metallization using FBH’s Ir-sputter gate technology, which allows an increase in gate metal thickness from the current 0.4 μm to approximately 1.0 μm for the transistors under investigation. This optimization leads to a substantial 50% reduction in gate series resistance, resulting in significant improvements in the RF performance. Specifically, the devices achieve 20% higher output power density and 10% better power-added efficiency at 20 GHz and V ds = 20 V. The decreased gate resistance enables new degrees of freedom in design, such as longer gate fingers and/or shorter gate lengths, for more efficient power cells operating in this frequency range.


Introduction
The K and Ka bands (18-40 GHz) include the majority of targeted frequency range 2 (FR2) in the millimetre wave range for 5G telecommunication systems [1,2].GaN heterojunction field effect transistors (HFET)s developed at FBH technology have demonstrated output power capabilities of up to 2.0 W mm −1 at 20-30 GHz for such applications.However, in order to further enhance these devices, downscaling of the transistor dimensions becomes necessary.Meanwhile, it is known from CMOS technology [3] that the radio frequency (RF) performance of transistors in smaller gate dimensions can be limited by gate resistance.Small signal power gain, maximum oscillation frequency (f max ), and minimum noise figure (NF min ) are highly influenced by the resistive and capacitive parasitic elements associated with the geometrical dimensions of the HFETs such as the contact resistance (R c ), the Original content from this work may be used under the terms of the Creative Commons Attribution 4.0 licence.Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.gate resistance (R g ), the channel resistance (R i ), and the gatesource/drain capacitances (C gs /C gd ) [4][5][6] as can be seen from equations (1)- (3), where f is the frequency, f t the cut off frequency and g m the transconductance, This study focuses on reducing R g by increasing the gate metal cross-section.As shown in the equations, that this approach theoretically has the potential to achieve higher gain, higher f max , and lower noise figure.The reduced R g also enables a scaled gate metal length (L T ) and/or longer gate finger.Hence, novel optimized power cell designs for K/Ka-band GaN MMICs can be realized.
The easiest method to increase gate metal cross section would be to increase the gate metal length (L T ) while keeping the metal thickness (H G2 ) constant.However, this would lead to an undesirable increase in the parasitic gate capacitances C gs and C gd .Thus, the gate metallization thickness has to be increased instead.However, the commonly used lift-off technique for gate metallization using an evaporated gate metal stack sets an upper thickness limit due to the cone-type shaped metallization inherent to this technology (figure 1(a)).To overcome this problem and to increase the gate metallization height from 380 nm to about 1000 nm without compromising the gate metal length (∼500 nm), Au electroplating followed by a thin Ni-layer was used in this work instead (figure 1(b)).This was done by developing an e-beam resist profile with fairly straight and vertical side-walls.Sufficiently smooth Au electroplating was achieved in a sulfidic electrolyte with a pH of 9.5 at 25 • C, ensuring that no damage is caused to the e-beam resist during electroplating.The electroplated Ni-layer on top of the Au layer serves as self-aligned dry etch mask for subsequently removing excessive Iridium metallization in conjunction with our Ir-sputter gate technology.Therefore, this metallization approach is compatible with the baseline of the FBH K/Kaband monolithic microwave integrated circuit (MMIC) technology with sputtered-Ir gates [7].Hence, the unique advantages of Ir Schottky gates in terms of lifetime and reliability of the devices are maintained.In this work, the fabricated devices with gate lengths of 100 nm and 150 nm, using the proposed approach and the FBH baseline technology, are evaluated in terms of their DC and RF characteristics.The device results as compared to devices with the traditional lift-off gate show that a significant reduction of 50% in gate series resistance led to notable improvements in RF performance.Specifically, for 4 × 75 µm transistors with a gate length of 150 nm, the reduced gate resistance results in an enhanced output power density from 2.0 to 2.4 W mm −1 and a power-added efficiency (PAE) increase from 33.1% to 43.3% at 20 GHz in the optimized technology.

Fabrication of AlGaN/GaN HFET
The transistors were fabricated on two nominally identical semi-insulating SiC substrates with MOVPE-grown epitaxial GaN HFET layers.These layers comprise a 50 nm AlN nucleation layer, 1.3 µm Fe-doped GaN buffer, 650 nm GaN channel, 10 nm Al 0.28 Ga 0.72 N barrier, and 2 nm Si-doped GaN cap layer, resulting in a two-dimensional electron gas (2DEG) channel with approximately 450 Ω/□ sheet resistance.The fabrication process involved several steps: ohmic contacts formation, deposition of a 150 nm silicon nitride passivation layer using PECVD system, device isolation by multiple energy N + implantation and gate contacts formation with the following procedure: The gate region is patterned using e-beam lithography (ZEP 520 A resist).Subsequently, SiN x was etched using SF 6 -CHF 3 at 300 W inductively coupled plasma (ICP) and 20 W high frequency (HF) power to form a slanted gate trench [8].Afterwards, a thermal treatment is conducted at 500 • C to mitigate potential damage caused by plasma etching to the semiconductor surface.This followed by sputtering iridium (50 nm) as Schottky contact all over the wafer.Thus, at this stage, the Ir layer can act as plating base metallisation.After these steps, the gate module was formed according to the FBH base line technology using a bi-layer ebeam resist (PMMA 50 K/950 K ∼ 500/300 nm) and evaporated gate metallization (Ti/Au/Ti/Ir 20/280/30/50 nm) for wafer W1, shown in figure 2(a).
For wafer W2, a new resist profile (PMMA 950 K ∼ 1100 nm) was developed (figure 2(b)) to maximize the increase in gate cross-section i.e. reduction in the gate resistance.This was followed by Au electroplating (∼900 nm) in a sulfidic electrolyte (11 g l −1 gold concentration) and Ni electroplating (∼100 nm) as an etch stop layer for the later Ir back-etch process.During the plating, wafers were located upside down and electrolytes were pumped onto the wafer to maintain a uniform fluid flow at the wafer surface.This approach, combined with a low current density of 1 mA cm 2 , guaranteed optimal surface roughness and thickness uniformity over the wafer.After gate formation on both wafers, the excess sputtered iridium was etched with Cl-based ICP dry etching, while the gates were protected by titanium in wafer W1 and plated nickel in W2.The fabricated devices with 1 µm thick electroplated gates are shown in figure 3. The gate-head length of the electroplated gates on W2 targeted about 500 nm while for the reference wafer W1, it is 500 nm at the bottom and 250 nm at the top of the gate metallization.Finally, the fabricated transistors on both wafers were characterized through RF and DC electrical measurements.The measurements were performed on transistors with gate lengths of 150 nm and 100 nm, source-gate distance of 0.5 µm, and drain-gate distance of 2.0 µm.

Results and discussion
The sheet resistance of gate metallization was extracted from process control monitoring structures using four-probe measurements.Figure 4 verifies that the gate metal sheet resistance was reduced by approximately 40% from 171 mΩ sq −1 in the FBH baseline technology (W1) to 104 mΩ sq −1 in the electroplated gate technology (W2).This improvement, as theoretically discussed earlier (equations ( 1)-( 3)), is expected to contribute to enhanced RF performance.Additionally, the 8.6 Ω/□ standard deviations in the sheet resistance of W2, attributed to variations in thickness or roughness across the wafer, closely DC measurements were carried out on 2 × 50 µm transistors with 150 nm gate length from both wafers under study and output characteristics are presented in figure 5. Additionally, important DC parameters are summarized in table 1 including the mean value of parameters such as the maximum drain current (I ds-max ), the gate-leakage current (I g-off ), the maximum extrinsic transconductance (g m ) and the Schottky barrier height (Φ b ).
As observed, the optimisation does not cause significant alternations in most aspects, however, the gate leakage has been increased by two orders of magnitude for the electroplated gates.This higher leakage in wafer W2 cannot be explained by variation in Schottky barrier height.In fact, these results confirm that the formed Schottky contact by sputtered Ir was not affected by the dissimilarities in the gate fabrication technology and Φ b has similar value for both wafers.Therefore, the observed increase in gate leakage in wafer W2 is likely related to the differences of the internal mechanical stress of the two metallization approaches.The presence of mechanical stress in the evaporated metal used in wafer W1 (more than 2.0 GPa compressive stress) and its absence in the electroplated metallization of wafer W2 may contribute to this phenomenon.Additionally, it is important to note that the gate leakage in wafer W2 exhibits one order of magnitude higher thermal sensitivity i.e. increasing during tempering steps in FBH fabrication technology (3 times, 45 min at each 350 • C), further emphasizing the impact of mechanical stress on this characteristic.To fully understand and analyse this effect, further investigation and statistical analyses are required.However, previous work conducted on FBH devices have already established the influence of induced mechanical stress through passivation layers and/or gate metallization on GaN HFETs' characteristics, such as gate leakage and threshold voltage [9,10].Earlier studies have demonstrated that mechanical stress induced during the fabrication process was transferred to the epitaxial layers beneath the gate region   [11].In the case of W1, the strained gate metal transfers compressive mechanical stress into the piezoelectric AlGaN/GaN epitaxial stack.This theoretically leads to a reduction in electron density under/edges of the gate contacts [12].Therefore, the observation of a lower gate leakage current in W1 is consistent with our previous observations of the reduced 2DEG electron density due to compressive stress.In order to analyze the impact of the new electroplated gate module on the transistor's performance, R g and f max for 2 × 50 µm transistors were extracted from S-parameter measurements from 50 MHz to 50 GHz and for V ds = 15 V. Figure 6(a) shows the mean value of the extracted gate resistance for both gate lengths and both technologies.This result indicates that scaling the gate length from 150 to 100 nm leads to 17% and 19% lower R g in wafer W2 and W1 respectively.Comparing both metallization technologies, it can be observed that R g decreased significantly by about 50%-55%, dropping from 7.5 Ω in W1 to 3.4 Ω in W2.
The decreased gate resistance directly translates into higher values for the maximum oscillation frequency (figure 6(b)).For both gate lengths, f max is increased by at least 10 GHz for the electroplated gate technology.According to figure 6(b), the higher R g in 100 nm devices from W1 has halted improvement in f max .These observations are consistence with equation ( 2), which shows a tradeoff between cut off frequency, gate-drain capacitance and gate resistance.This implies that although a shorter gate length leads to a higher f t and smaller C gd , the gate resistance can act as a bottleneck in achieving a higher maximum oscillation frequency.Furthermore, in this study, we conducted load-pull measurements at a 20 GHz, 20 V bias point on 4 × 75 µm transistors with a gate length of 150 nm to compare the different gate technologies.Figure 7 clearly demonstrates that the utilization of the electroplated gate module led to significant enhancements in both, the maximum output power density and PAE, with values increasing from 2.0 W mm −1 and 33.1% for wafer W1 with FBH baseline technology to 2.4 W mm −1 and 43.3% for W2 with the electroplated gate module.Realizing a 10% enhancement in PAE at 20 GHz represents a notable improvement.When factoring in the elevated gate leakage current in W2, it suggests the potential for an even higher efficiency under similar leakage conditions.This implies that the reduction of lateral voltage drop along the more conductive gate electrode outperforms potential leakage issues and thus results in an increased PAE.
These findings highlight the critical role of the gate resistance in the RF performance of GaN HEMTs.The incorporation of a low-resistive gate module outperforms the conventional gate contacts, resulting in superior large signal performance.It is important to note that these improvements are expected to be more pronounced for transistors with shorter gate lengths and/or longer gate fingers, further emphasizing the potential optimizing the RF performance with provided additional flexibility in design.

Conclusion
In this work, electroplating was introduced as a new gate-head fabrication technology for low-loss T-gate structures.The gate resistance in GaN HFETs with 2 × 50 µm gate periphery and 150 nm gate length was reduced by 50%.This improvement resulted in 20% higher output power density and 10% better PAE at 20 GHz and V ds = 20 V for 4 × 75 µm transistor.The results demonstrated that by utilizing the reduced gate resistance technology, longer gate fingers can be used without degrading f max and large signal performance.This is particularly true for shorter gate lengths.These findings are of significant technical and practical importance: they demonstrate that despite of the still higher gate leakage current of the developed technology, there the benefits in term of an overall improved PAE are already clearly visible.As a result, these advancements enable more efficient power cells in the K and Ka frequency range and above.

Data availability statement
All data that support the findings of this study are included within the article (and any supplementary files).

Figure 1 .
Figure 1.Transistor cross sections are presenting FBH current gate technology versus the optimized version.

Figure 2 .
Figure 2. Comparing resist profiles for lift-off and electroplated gate patterning by SEM imaging: (a) bi layers PMMA resist with undercut ⩾ 200 nm in FBH standard lift off technology (b) developed single PMMA layer using proximity correction to achieve a low undercut of less than 50 nm (ideal for electroplating).

Figure
Figure Electroplate gate structures: (a) 2 × 50 µm transistors with the developed gate technology (b) image is presenting the selected area in part a which shows a gate pad with about 900 nm thickness.

Figure 6 .
Figure 6.Comparison of wafer W1 and W2 in terms of extracted small signal parameters from 2 × 50 µm transistors.(a) Gate resistance versus gate length (b) f max versus gate resistance.The dashed line in part b represents the average fit of the extracted values.Additionally, arrows illustrate the trend in f max by changing gate length from 150 to 100 nm.

Figure 7 .
Figure 7. Compression of wafer W1 and W2 in terms of load-pull measurements at 20 GHz and V ds = 20 V for 4 × 75 µm transistors with L G = 150 nm in terms of (a) output power density and (b) PEA tuned for maximum efficiency.